Forum: FPGA, VHDL & Verilog URGENT! Gate-lvel Netlist

von Karthiga G. (karthiga05)

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Hi. Can someone please help me explain what is gate-level netlist and 
what is it used for? urgently need it. thanks!

von Duke Scarring (Guest)

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A gate-level netlist contains only LUTs and FlipFlops (in case of an 
FPGA) the basic chip elements. You can use it for timing simulation or 
to check the synthesiser result.
If you have an strictly synchronous design, you can skip this kind of 
simulation normally.



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