I am trying to burst data out of my Cyclone II via a FTDI FT2232H -Chip
in FT245 FIFO mode (see FT245_fifo.png) as described in the FTDI
Application Node 130 (see burst.png):
A write operation can be started when TXE# is low. WR# is brought low when the data is valid.
A burst operation can be done on every clock providing TXE# is still low. The external system must monitor TXE# and its own WR# to check that data has been accepted.
Both TXE# and WR# must be low for data to be accepted.
Debugging my design shows me, that the signal sequences fit the
desciption (see ft232_burst.png), but I only receive 1 byte at the PC
side, in fact the last one that is on the bus before WR# goes high (or
What am I doing wrong? Am i missing simething?