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Hi guys, I read that when an op amp is driving a capacitive load, its transfer function is disturbed, a new pole is added into it which reduces the phase margin. This leads to instability at the output voltage of the op amp. Now I'm wondering if this problem occurs only when the input voltage of the op amp is AC, or also for DC? I have an op amp (Voltage follower), which has a cap of 10uF in fornt of it. Do you think this cap will influence its stability even if the input voltage is DC, and I need to use a compensation method? Thx
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If you have a stability problem, you will see oscillations at the output. The type of input voltage doesn't matter. Or your settling behaviour is bad when applying a step at the input. In the datasheet there should be a value for maximum capacitive load. The op amp can handle a greater load than written in the datasheet when putting a resitor in series to the capacitance. But then the maximum output current and slew rate are reduced. You will find opamps whitch can drive unlimited capacitive load, but then there could be worse values for offset voltage, 1/fnoise etc. You should compare.
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>Do you think this cap will influence its stability even if the input >voltage is DC, and I need to use a compensation method? Yes, of course. There's always enough noise within the circuit to make the OPamp finally run into wild oscillations. And do not forget the voltage step when turning on the supply voltage. Remember, there are some OPamps which can directly drive such high loads though.
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Thank you for your answer. I read a lot of technical papers in the net, explaining what happens when an op amp is driving a cap load. But I'm not sure if this problem occcurs only when the input is AC, or regardless of the input... So when we talk about bause diagramm for phase and amplitude, and phase margin etc... which frequency are we talking about, isn'it the freq of the inout signal to the op amp? Thx
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I'm using TLV4110 op amp. I'm using it as voltage follower. In the data sheet I found the following graph. Could you help me interpret it? As far as I know, the bigger the phase margin, the more stable is the output of the op amp. On the other side, according to this graph, the stability depends on the output resistive load too...
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In your circuit is always noise and noise is broadband (as Ina said). So you will never have only a dc input voltage. And even your supply isn't clean and constant. It includes noise and ripples from ac input or even peaks from switching power supply.
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>In the data sheet I found the following graph. Could you help me >interpret it? It just states, that you shall insert a series resistor of at least 20R, if you intend to drive large capacitive loads. Tell us in more detail what you plan to do...
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You can read from the diagramm: Load resistance has a small influence on phase margin too. But the load capacitance is dominant. For higher values you have to put a resistor in series (RNull). Have you had a look at the application information at page 12? There's even given a value. You can try.
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Guys, thank you very much for all your answers. What I'm intending to do is, to measure the current consumption of a uprocessor. So I have to take care abbout the voltage regulation of it too. So now I assume that my uP (Load) is my resistor R2. The current consumed by R2 s the same one flowing through R1 (shunt). Later I will amplify the voltage drop across R1 to know how much current is flowing. So The caps C1 and C2 are decoupling caps, needed by the uP. In my testing board, I used a battery at Vg1. So its voltage is pretty much stable. At the output of the op amp, the voltage is also pretty much stable, BUT the voltage drop across R1 is not stable!!! Unfortunately I can't use a series resistor of 20 Ohm, as stated in the data sheet, because imagine when my uP is consuming 100mA, I will have a voltage drop of 2V across that resistor, and that is too much!
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In http://www.analog.com/library/analogdialogue/archi... some compensation methods are proposed. Let's concentrate about Snubber Network which seems to be a very well known method, It is said that the values of Cs and Rs are determined. based on the freq of the signal. I attached the sweep of the voltage across the shunt resistor in the feedback loop. The signal is periodic, and has a period of 133kHz.
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>What I'm intending to do is, to measure the current consumption of a >uprocessor. So I have to take care abbout the voltage regulation of it >too. The approach you follow is highly unsuited. There are way simpler circuits to accomplish that. Measure the voltage drop across the shunt resistor by using a "high side current monitor", for instance. Google for that.