A Tiny FPGA design software with modern interface

Guest #2236428
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Well the application looks nice - really I see that you must have put 
some work into it.
I did not test it so far as I don't quite get what the advantage of this 
tool is compared to typing Code directly (s. the other thread it was 
basically already explained there).


You only show ultra simple examples (a counter... c'mon) - THAT is too 
easy even for beginners.

What is hard is to keep the overview of a full system with dozens or 
hundreds of such modules and to make them work together -  and simulate 
that properly.


And $100 for the Students license is waaaay to much for the average 
Student as they are used to get such small tools for free.
And then they shall also share the designs with you after they paid 
$100?
Sorry but WTF?!
That is a license term you can use with BETA TESTERS but not with actual 
customers... lol
Guest #2236558
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Thank you for your suggestions. The advantage of this tool is design 
with visualization. Coding will be fine for verilog design, but compare 
reading code with seeing the model, the second one would be better. This 
tool also can reduce the mistakes in your design before going to code 
level. At the same time, it is a small tool, the biggest advantage is it 
will be used in PDA
systems.


The Robei FPGA design tool is targeting to entry level customers and try 
to reduce the knowledge requirement of FPGA. With this tool, high school 
student can play with FPGA with a little knowledge of verilog.

We break down complex system into small reusable models, so complex 
system will works fine.

The requirement of contribute code is for beta testers, and this 
requirement is no longer for student as we do not asking for code in 
fact. I need to check the released version, and that sentence should be 
deleted already. Thank you for your suggestion, if the sentence is still 
there, I can give a license for free.

I provided a lot of free licenses for those customers who send feed back 
to me. The software will keep improving and more features will be in the 
next version.
Guest #2237967
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Oh hey thanks for the offer :-) , but I just wanted to help you and 
emphasize again where the Problems are (most of this was already 
discussed in the other thread).
I already have such a graphical Tool - but it's way more powerful (and 
comes with extensive examples! hint *hint*).
It's more expensive, but with your old pricing it was not thaaat big 
difference.
New pricing is a lot more reasonable.
Guest #2239151
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You should think of the main aspects, werea graphical tool will help:

1) overview
signals must be able to easily move between hierarchies.
hierarchies must by virually installed by wrapping components
and it must be able to undo this
design from top to buttom, not as usual from buttom to top by creating 
symbols and ading them together

2) Reduce Typing
-> automation of entity copying and transformation to components, 
mappings

when mooving out a component from a sub level, new signals must be 
invented to shift through the hierarchy
Guest #2239274
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Well, in its current state it would not be of much use for me - as I 
already said I have a very powerful tool for such things and much more 
(but even with this I preferr typing Code directly).
Another problem is I am using VHDL only! ;-)

But a good cheaper and less complex alternative that only focusses on 
top-down hirarchy design (what Mehlbuttel said) would be welcome anyway.
Guest #2244015
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I sold very few licenses, but I provide a lot of free licenses as the 
exchange of good suggestions. So I collected many useful suggestions, 
which I can realize them in the next version. That would be much more 
valuable than money.

Thanks!

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