Nested if rising_edge(clk) statements?
Guest
#2228026
I've come across this in some code, and I'm really curious what it does:
if rising_edge(clk) THEN
--do some flip flop things
if rising_edge(clk)THEN
--do other flip flop things
end if;
end if;
Does this code make it take 2 rising edges to get to the "inner" if
statement? or is the second if statement completely redundant?
Thanks, any help is appreciated.
Guest
#2228226
the second statement, reacts on the same condition, so it is redundant and can be removed
Guest
#2228366
No this wait-statement cannot be just removed because it is in no wy redundant. The simulator awaits there the next rising edge to process the next few statements. The resulting hardware realisation depends on your specific synthesiser. It is not unlikely that this is not synthesisable, too.
Guest
#2228378
Ah, sorry, I am just a bit too tired and read an wait until instead of an if.. then. You are right, of course! ReplyPlease log in before posting. |