Hi, I've generated a memory interface for a ML605 board using MIG 3.6 from ISE 12.3. The system clock is 200 MHz and Burstwidth is configured to 8. I've implemented custom logic for controlling the generated UI. My task is to perform one 2x256 bit write and as many read commands as possible in a period of 100 ns. The image attached depicts such a use case, one write to an address and three reads back to back (the read adresses vary, this was not implemented in the simulation where the pic was taken, but has no influence on the issue). As demanded by the MIG documentation, one has to wait for app_rdy being asserted at the same time as app_en for a command being performed properly. But obviously, my command pattern is not such one the UI likes best and therefore app_rdy is only asserted sporadically. So the whole write/tripleread action takes more than 100 ns. If I only perform one write and one read alternating, the UI trains itself to that use case and asserts app_rdy nearly seamless after some µs. But as already mentioned, I need several reads after the write, and performance is too bad already when performing two reads after the write. Now my question: Which command pattern is more performant for such a use case? Shall I include waitstates between the read commands or something? Many thanks in advance!