i need help for my project.

Guest #2017587
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I'm afraid your question is incomplete. So I'm now guessing:

- I believe you have an eight bits wide unsigned input vector.
- I also estimate that your seven segment displays are connected to your 
FPGA 1:1 and thus do not need to be multiplexed.

If I'm right with both estimations, the simplest way for you to do it is 
the following:

- In your thoughts, split up your eight bits wide vector into two four 
bits wide vectors, each of them serving one display.
- For each four-bit-vector, instantiate a truth table converting all 
input value patterns possible (0..15) into their correct representations 
on your display.

I suppose you're a VHDL beginner. Here's a good tutorial: 
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html

The truth tables could be implemented with a SELECT or a CASE statement, 
for example.

Patrick

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