I'm afraid your question is incomplete. So I'm now guessing:
- I believe you have an eight bits wide unsigned input vector.
- I also estimate that your seven segment displays are connected to your
FPGA 1:1 and thus do not need to be multiplexed.
If I'm right with both estimations, the simplest way for you to do it is
- In your thoughts, split up your eight bits wide vector into two four
bits wide vectors, each of them serving one display.
- For each four-bit-vector, instantiate a truth table converting all
input value patterns possible (0..15) into their correct representations
on your display.
I suppose you're a VHDL beginner. Here's a good tutorial:
The truth tables could be implemented with a SELECT or a CASE statement,