i need help for my project.

Guest #2017587
Rate this post
• ▲ useful
▼ not useful
I'm afraid your question is incomplete. So I'm now guessing:

- I believe you have an eight bits wide unsigned input vector.
- I also estimate that your seven segment displays are connected to your 
FPGA 1:1 and thus do not need to be multiplexed.

If I'm right with both estimations, the simplest way for you to do it is 
the following:

- In your thoughts, split up your eight bits wide vector into two four 
bits wide vectors, each of them serving one display.
- For each four-bit-vector, instantiate a truth table converting all 
input value patterns possible (0..15) into their correct representations 
on your display.

I suppose you're a VHDL beginner. Here's a good tutorial: 
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html

The truth tables could be implemented with a SELECT or a CASE statement, 
for example.

Patrick

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.