Hi I have started on this project which is described in the attachment document. Now i tried using two process: one for LOGIC and one for ARITHMETIC. My problem is can someone give to another way of doing this because i synthesis the code on the attachment and it gives me the following errors. The reason for these errors is that i am using A and B in two process which conflicting.
Guest
#2015911
Which errors do you mean? The sensitivity list of both processes is incorrect, which will cause problems during the simulation. The LOGIC process doesn't use the sCIN signal, so this signal can be removed from the list. The bigger problem is the missing signals in the sensitivity list of the ARTH process. You'll need to add all signals that are used on the right side of a signal assignement to the sensitivity list of a combinatorial process (A, B, and cIN are missing in this case).
oops, sorry about that, well this is the revised version of it: the error i get is the following: ERROR:Xst:528 - Multi-source in Unit <part3> on signal <final<3>>; this signal is connected to multiple drivers. ERROR:Xst:528 - Multi-source in Unit <part3> on signal <final<2>>; this signal is connected to multiple drivers. ERROR:Xst:528 - Multi-source in Unit <part3> on signal <final<1>>; this signal is connected to multiple drivers. ERROR:Xst:528 - Multi-source in Unit <part3> on signal <Madd_final>; this signal is connected to multiple drivers.
Guest
#2015934
You assign two different values to the signal G. One in the concurrent statement "G <= final(3 downto 0);" and one in the ARTH process. You don't need the first assignement and the final signal isn't needed at all. Just enlarge the G signal to get the carry bit. Another thing you might consider is removing the sCIN signal and just using the sel signal in the case statement in the ARTH process. If you look at the cases you'll see that the result is incremented by one each time cIN is '1'.
in order to enlarge it don't i have to do "G <= ('0' & A) + ('0' & B);"
i used the final signal to declare how many bits the cOUT and F are
going to have. So isn't this required?
Guest
#2017357
You still have to extend the operands, but not in the concurrent signal assignement. Use similar assignments in the ARTH process. If you extend the G signal by one bit you can assign G(4) to cOUT and G(3 downto 0) to F, when the apropriate mode is set.
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