Hello experts, I am stuck in doing a VHDL testbench. My VHDL code works just fine, but the problem now is that I cannot make the right testbench. * the first problem is the clock, I made two seperated processes, one for clock and the other one for setting different valuse for the input. The clock process does not work !! the simulation does not show any change in the clock signal. * Same problem for reset, I put the reset signal in the second process, and it doesn't work propely. * regarding setting the values, for the input I used for loop as follows for j in 0 to 7 loop X(i) <= '1' ; wait for 10 ns; end loop; and this also doesn't work properly. any help is truley appreciated.
for j in 0 to 7 loop X(i) <= '1' ; --- should this be a X(j) or am I missing some code? wait for 10 ns; end loop;
> any help is truley appreciated. Pls show your code... > The clock process does not work !! the simulation does not show any > change in the clock signal. Do you simulate the testbench or your VHDL-Module?
can any1 suggest good book that teaches vhdl testbench from basic. if possible then share the link of the same.
Okay I can't help you with a book I only know german vhdl books but this link seems to be good: http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html And for your problem with the clock an reset signal. When I write a Testbench I do it like this:
ARCHITECTURE DUT_tb_BEHAV OF DUT_tb IS CONSTANT PERIOD : TIME := 500ns; -- initiate the time value for the system clock BEGIN -- Creating the system clock cycles PROCESS BEGIN clock <= '0'; WAIT FOR PERIOD/2; clock <= '1'; WAIT FOR PERIOD/2; END PROCESS; -- Creating the asynchronous clear signal PROCESS BEGIN resetn <= '0'; WAIT FOR PERIOD*2; resetn <= '1'; WAIT; END PROCESS; END ARCHITECTURE;
I use the following one-liners for signal generation:
constant tb_clk_period : time := (1 sec / 50_000_000); signal tb_CLK : std_logic := '0'; signal tb_RESET : std_logic; [...] tb_CLK <= not tb_CLK after tb_clk_period / 2; tb_RESET <= '1', '0' after 10 * tb_clk_period;
Hi QTX, "tb_CLK <= not tb_CLK after tb_clk_period / 2;" will not generate a periodic clock, it'll generate a rising edge after tb_clk_period / 2. Use a Process instead and it'll work.
@wollibk: > "tb_CLK <= not tb_CLK after tb_clk_period / 2;" will not generate a > periodic clock, it'll generate a rising edge after tb_clk_period / 2. Check at your simulator first, before post nonsense... Duke
i need to produce a signal with rising edge alone of 1 micro second in test bench, please help.
Pls. do not attach your question to any old thread. Instead start a new thread with your question... And then show what you have, and ask a specific question concerning your problem. This forum here is not for stupidly solving homework...