VHDL testbench

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 for j in 0 to 7 loop

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       X(i) <= '1' ;     --- should this be a X(j) or am I missing some code?

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       wait for 10 ns;

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 end loop;

> any help is truley appreciated.
Pls show your code...

> The clock process does not work !! the simulation does not show any
> change in the clock signal.
Do you simulate the testbench or your VHDL-Module?

Okay I can't help you with a book I only know german vhdl books but this 
link seems to be good:
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html

And for your problem with the clock an reset signal. When I write a 
Testbench I do it like this:

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ARCHITECTURE DUT_tb_BEHAV OF DUT_tb IS

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CONSTANT PERIOD  : TIME := 500ns;  -- initiate the time value for the system clock

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BEGIN

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  -- Creating the system clock cycles

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  PROCESS 

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  BEGIN

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    clock <= '0'; WAIT FOR PERIOD/2;

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    clock <= '1'; WAIT FOR PERIOD/2;

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  END PROCESS;

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  -- Creating the asynchronous clear signal

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  PROCESS

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  BEGIN

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    resetn <= '0'; WAIT FOR PERIOD*2;

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    resetn <= '1'; WAIT;

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  END PROCESS;

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END ARCHITECTURE;

Greetings Phil

I use the following one-liners for signal generation:

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    constant tb_clk_period     : time := (1 sec / 50_000_000);

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    signal   tb_CLK            : std_logic := '0';

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    signal   tb_RESET          : std_logic;

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[...]

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    tb_CLK   <= not tb_CLK after tb_clk_period / 2;

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    tb_RESET <= '1', '0'   after 10 * tb_clk_period;

Duke

Hi QTX,

"tb_CLK   <= not tb_CLK after tb_clk_period / 2;" will not generate a 
periodic clock, it'll generate a rising edge after tb_clk_period / 2.

Use a Process instead and it'll work.

@wollibk:
> "tb_CLK   <= not tb_CLK after tb_clk_period / 2;" will not generate a
> periodic clock, it'll generate a rising edge after tb_clk_period / 2.
Check at your simulator first, before post nonsense...

Duke