Hello everyone, I am new to VHDL and I like it ! I have a question about usage of signals in VHDL, I have been told that it is more conenient to use signals to connects ports, instead of connecting ports directly. Now I wonder why is that ?! and how to do it a sequential process ? when should the value from the input port should be taken into the signals ? the signal passes the value to the output with the clock edge, so what about the input ?!! Thanks in advance Young
> I have been told that it is more conenient to use signals to connects > ports, instead of connecting ports directly. In my opinion only output ports are affected, because you cannot read back an out port. So given this short sample:
entity runningLED is
Clk : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR(7 downto 0)
end runningLED ;
architecture Behavioral of runningLED is
signal LEDs : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
wait until rising_edge(clk);
if (LEDs="10000000") then -- this would not be possible on the output port "LED"
LEDs <= "00000001";
LEDs <= LEDs(6 downto 0) & '0';
LED <= LEDs;
thanks so much for your reply. I don't understand why the LED <= LEDs; is not in the end of the process! the output port should take the value each clock, right ?! I believe it should be as a part of the process
If you put the assignment inside the process, you would have another flipflop generated. Here, this assignment is just connecting the output of the internal register, namely LEDs, which updates with each clock to the output of the entity. This is not different to put a wire between the output of an IC to the actual connector on the edge of your board. So, a combinatorial assignment without involving the clocked process is what you need in here.