module count (clk, rst, enable, cnt);
input clk, rst, enable;
output [3:0] cnt;
reg [3:0] cnt;
always @(posedge clk or posedge rst) // async active high reset
begin
if(rst)
cnt <= 0;
else if(enable)
cnt <= cnt + 1;
end
endmodule
===================================================================
What is the testbench for this code??
This should be a good starting point for you but you definitely should
make some exercises by modifying it. You could start by applying
comments to the sections below and posting the result.
HTH, Harald
----(snip)----
`timescale 1ns/1ps;
module top;
reg clock;
reg reset;
reg enable;
wire [3:0] counter;
always
begin
#5 clock = !clock;
end
count count_1
(
.clk(clock),
.rst(reset),
.enable(enable),
.cnt(counter)
);
initial
begin
clock = 0;
reset = 1;
enable = 0;
repeat (2) @(posedge clock);
reset = 0;
repeat (3) @(posedge clock);
enable = 1;
repeat (17) @(posedge clock);
if (counter != 4'h1)
begin
$display("error, counter value is not 1 but should be");
$stop;
end
$display("test ok");
$stop;
end
endmodule
----(snap)----
** Error: D:/Linda/testing/counter_tb.v(1): near ";": syntax error, unexpected ';', expecting "class" ======================================================================== got error...
expecting "class" ??? What tool do you use to compile the counter and the testbench?
Thank you... i figure out liao...
thank you so much... but the way what is this i need to understand
=> repeat (2) @(posedge clock);
reset = 0;
repeat (3) @(posedge clock);
enable = 1;
repeat (17) @(posedge clock);
if (counter != 4'h1)
begin
$display("error, counter value is not 1 but should be");
$stop;
end
$display("test ok");
$stop;
end
thank you
> but the way what is this i need to understand > => repeat (2) @(posedge clock); I do not know Verilog, but i would interpret this as "wait for 2 rising edges of clock" I would recommend you a book for absolute beginners... :-/
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