Forum: FPGA, VHDL & Verilog Loss of lock in the PLL of ALTLVDS_Rx (Cyclone III)

Author: Andrew K. (andrewk)
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I have two similar boards based on Cyclone III.
My project works in both boards. This project performs exchange of data 
between boards with LVDS (physical link is made by SATA cable and 
Two boards are connected by two SATA cables.
Accidentally (it may be very sparse), I see the loss of lock in the PLL 
of ALTLVDS_Rx (I capture falling edge of output "rx_locked").

What can be the reason of it ?

Author: Harald Fluegel (Guest)
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Clock jitter, most probably. Can you tell more about the project 
(frequency, SERDES, ...)?


Author: Andrew K. (andrewk)
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thank you for your reply.

Some details about my project:
SATA cable consists of two diff pairs. And I use one of them to transmit 
data and the second pair to transmit clock.
One SATA cable is assigned to transmit from board "A" to board "B". The 
second SATA cable is assigned to transmit from board "B" to board "A".
Termination is correct, 100 Ohm SMT resistors (for data and clock pairs 
respectively) at the receiver.
Data rate is 160 Mbps.
Unfortunately, I have no special oscilloscope to view waveform at the 
receiver. Before production of PCB simulation was made to set impedance 
of pathes to 50 Ohm.

Also, Quartus II posts message after compilation:
Critical Warning: PLL"altlvds_tx0:inst23|altlvds_tx:altlvds_tx_compo 
nent|lvds_tx_9hi1:auto_generated|lvds_tx_pll" input clock inclk[0] is 
not fully compensated because it is fed by a remote clock pin "Pin_90".

It may be the possible reason of loss of lock in the PLL of receiver. 
But Pin 90 is dedicated clock input (CLK14) in EP3C16Q240C8 and I 
connected external clock generator (20 MHz) to pin 90.

How can I determine a dedicated (not remote) clock input pin for PLL 
used in ALTLVDS_Tx?

As external clock generator I use GXO-7531 (Golledge): 20 MHz, stability 
100 ppm.

May be 100 ppm is bad with relation to jitter ?

Author: Sym (Guest)
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The thing with the compensation is: You have selected a specific PLL 
mode (e.g., source synchronous). If you don't use the correct clock 
input pin for the PLL, it can't compensate for the internal delay and 
hence the clock might not be synchronous to the clock source.
You'll find the correct clock input pin by looking it up in the data 
sheet. You should use PLL input and output belonging to the same PLL 
block. Not every clock input is directly fed to a PLL.

100 ppm does not define phase noise, just bounds for the frequency. 
Typical is 20-50 ppm, 100 ppm is rather high. You need to take the 
freuquency offset into account for the elastic buffering between the 
clock domains. Typically, a standard XO is fine. You could try reducing 
the loop bandwidth.

I suspect that the reason is that some clock edges are lost causing the 
PLL to lose lock. Check for this first.

Author: Harald F. (hfl)
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As far as I can see the error message is related to the transmit PLL. It 
seems you are using the Altera Serdes macros what means that the low 
speed clock is sent from the tx device to the rx device. So, if the 
receiver PLL looses lock then the low speed clock might be disturbed in 
any way. Compensation issues for the high speed clock are not of 
interest in that case.

I agree on Sym: Try reducing the loop bandwidth. It's a mess you don't 
have an appropriate scope. Do you use on-chip termination at the tx side 
or external Rs? What IO standard have you selected?


Author: Andrew K. (andrewk)
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Harald, Sym,
thank you for your help.
Your comments are very useful because it is my first project with LVDS.

How can I reduce the loop bandwidth in PLLs of ALTLVDS_Tx and 
(I use internal PLLs in these modules. Therefore I have no control to 
change the loop bandwidth).
As I use internal PLLs for ALTLVDS_Tx and ALTLVDS_Rx their operating 
modes and settings are inaccessible for me to change them.

I use true-LVDS transmitters in EP3C16Q240C8. Therefore there are no 
external Rs at Tx side.

Also, how can I check the use of on-chip termination at Tx side?

In assignment editor (Quartus II) I/O standard "LVDS" is set for both Rx 
and Tx pins (data and clock pairs).

Thank you.

Author: Andrew K. (andrewk)
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....about clocking scheme of my project:
External clock generator is connected to pin 90 of EP3C16Q240C8. In 
Quartus II the signal from pin 90 feeds the main PLL which generates 
internal clocks for my project. Also, the signal from pin 90 is 
connected directly to input "tx_inclock" of ALTLVDS_Tx.
As to ALTLVDS_Rx, its input "rx_inclock" is defined as differential 
(LVDS) and connected to pins DIFFCLK_xx (p and n) of EP3C16Q240C8. 
Therefore, PLL of ALTLVDS_Rx receives its clocks from another board 
(i.e. from output "tx_outclock" of ALTLVDS_Tx of another board).

Harald, I think you are right that "...the error message is related to 
the transmit PLL".


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