Hello,
I am trying to implement a resolution function for std_logic_vector in
VHDL... Synthesize is ok but behavioral simulation gives me errors...
I declared
signal a_temp : res_a STD_LOGIC_VECTOR (3 DOWNTO 0);
In my main code, i tried to assign different values to a_temp ('res_a'
is resolution function). Then i defined a package with the function
'res_a' in it as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package resolution_deneme is
type bit_4_array is array (natural range <>) of std_logic_vector(3
downto 0);
-- Declare functions and procedure
function res_a ( input_a : bit_4_array) return std_logic_vector;
end resolution_deneme;
package body resolution_deneme is
function res_a ( input_a : bit_4_array) return std_logic_vector is
variable a_temp : std_logic_vector(3 downto 0);
begin
-- do something
return a_temp;
end res_a;
end resolution_deneme;
As I said before synthesize is ok, but behavioral simulation gives me
the following error:
Signal cannot be unconstrainedERROR:Simulator:777 - Static elaboration
of top level VHDL design unit test in library work failed
And the error points the signal declaration line:
signal a_temp : res_a STD_LOGIC_VECTOR (3 DOWNTO 0);
What do you think the problem is? Did i make mistake in defining the
resolution function?
Thank you
Mete