Hi,

This is a query on Verilog usage. If this is not the appropriate forum
for this type of query, please ignore this request.

Can I use parameters as part of the size specification for a sized
number ? My simulator (gplcver), gives error. e.g. :-
***
parameter DATA_WIDTH = 8;

// o/p to external bus
assign data = (CS && !WR) ? data_out : DATA_WIDTH'bz;
***

I wish to avoid `defines in verilog source.

-- Thanks, V