Hi, i am doing vhdl code for eeprom for write operation. in that i try to simulate my coding i met with few problems. i use 2 process statement. 1st process depends on clk input. 2nd process depends on cyc. In the 2nd process it should consider two factors cyc and count. my code: entity eeprom1 is port( clk:in std_logic; sclut std_logic:='1'; ledut std_logic_vector(2 downto 0):="000"; sda:inout std_logic:='1'); end eeprom1; architecture Behavioral of eeprom is type arr is array (0 to 2) of std_logic_vector(7 downto 0); constant data:arr:=(x"15",x"00",x"f8"); signal ack:std_logic:='1'; signal cyc:std_logic_vector(4 downto 0):="00000"; signal count:std_logic_vector(6 downto 0):="0000000"; begin process(clk) --------1st process------ begin if (clk'event and clk='1') then count <= count + 1; if count <= 63 then scl<='0'; elsif (count >63 and count < 125) then scl <='1'; elsif(count=125)then cyc<= cyc+1; count<="0000000"; end if; end if; end process; process(count) ---------2nd process----------- variable bi:integer:=0; begin if (cyc=0 and count <70) then sda<='1'; led<="001"; elsif (cyc=0 and count >=70) then --start high to low--- sda<='0'; led<="010"; elsif (cyc>=1 and cyc<=9 ) then sda<=data(0)(bi); led<="011"; if(bi < 7) then bi:=bi+1; end if; elsif(cyc=10 ) then ack<=sda; led<="100"; elsif(cyc=11 ) then bi:=0; sda<='0'; led<="101"; elsif (cyc>=12 and cyc<=19 ) then sda<=data(1)(bi); led<="110"; if(bi < 7) then bi:=bi+1; end if; elsif(cyc=20 ) then ack<=sda; bi:=0; led<="111"; elsif (cyc>=21 and cyc<=28 ) then sda<=data(2)(bi); led<="000"; if(bi < 7) then bi:=bi+1; end if; elsif(cyc=29 ) then ack<=sda; led<="001"; elsif(cyc=30 and count >70) then sda<='1'; led<="010"; end if; end process; end Behavioral; expected result : sda = 1 until cyc =0 and count <70 sda = 0 at cyc =0 and count>70 sda =(sequence of data from constant array) at cyc >= 1 and <=9 . but the result not consider count value. so also declared 2nd process as process(cyc,count) now sda =(sequence of data from constant array) at cyc >= 1 and <=9 . sda not depend on cyc.it depends on clk input. so please clerify me. it will great help. advance thanx.
Guest
#1772673
> process(count) ---------2nd process----------- > variable bi:integer:=0; > begin > if (cyc=0 and count <70) then This process also depends on cyc and therefore the sensitivity list is incomplete. > so also declared 2nd process as process(cyc,count) This is a little bit more correct, but look at this:
1 | |
2 | |
3 | |
4 | |
5 | |
6 | |
7 | |
8 | |
9 | |
Although you (perhaps) will get a fine simulation, this will form a
combinatorial loop in a synthesized design. Because due to the use of a
variable the result of bi depends of the former value of bi. And so bi
should be placed in the sensitivitiy list also. But this is not possible
with variables... :-o
You can use counters like bi:=bi+1 only in clocked processes!!!
> sda not depend on cyc.it depends on clk input.
This usually is good and its called a synchronous desgin.