good morning, am obliged to define the type t_pnet_data before the architecture to be able to use it in ports types, this is a part of the code : library ieee; use ieee.std_logic_1164.all; subtype t_pnet_data is std_logic_vector(7 downto 0); type net_frame is record low : t_pnet_data; high : t_pnet_data; end record net_frame; entity pnet_write is port( p_net_data_in : in std_logic_vector(7 downto 0); p_net_data_valid : in std_logic; p_net_data_read : out std_logic; p_cpu_data_out : out std_logic_vector(7 downto 0); p_cpu_data_valid : out std_logic; p_cpu_data_read : in std_logic; p_cpu_parity : out std_logic; p_retx_data_out : out net_frame; p_retx_data_valid : out std_logic; p_retx_data_read : in std_logic ); end pnet_write; architecture write of pnet_write is begin - - - - - - and this the error : ** Error: C:/Modeltech_6.2d/examples/pnet_write.vhd(5): near "subtype": expecting: ARCHITECTURE CONFIGURATION ENTITY LIBRARY PACKAGE USE what can i do ?! best regards Wafa
You cannot define a type outside the entity- or architecture. When you need such a type, you have to define it in a package and "use" the package.
Create new file with
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | |
4 | package my_data_types is |
5 | |
6 | subtype t_pnet_data is std_logic_vector(7 downto 0); |
7 | |
8 | type net_frame is record |
9 | low : t_pnet_data; |
10 | high : t_pnet_data; |
11 | end record net_frame; |
12 | |
13 | end package my_data_types; |
In your design you write
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | |
4 | use work.my_data_types.all; -- <-- your package in standard library work |
5 | |
6 | entity pnet_write is |
7 | port( |
8 | p_net_data_in : in std_logic_vector(7 downto 0); |
9 | p_net_data_valid : in std_logic; |
10 | p_net_data_read : out std_logic; |
11 | p_cpu_data_out : out std_logic_vector(7 downto 0); |
12 | p_cpu_data_valid : out std_logic; |
13 | p_cpu_data_read : in std_logic; |
14 | p_cpu_parity : out std_logic; |
15 | p_retx_data_out : out net_frame; |
16 | p_retx_data_valid : out std_logic; |
17 | p_retx_data_read : in std_logic |
18 | );
|
19 | end pnet_write; |
To get more information, just type "vhdl package" in google ;)
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