Good morning, is it possible in an architecture to call a process several times only by changing its variables ?! for example, if i have a process called calculate calculate:process(A,B,C) begin C<=A+B; end process calculate; then i want to use the same process for D,E and F is it possible to call calculate without writing the instructions again? if its possible,how ? best regards Wafa

What you need is afunctionforcalculate. > calculate:process(A,B,C) > begin > C<=A+B; > end process calculate; > then i want to use the same process for D,E and F > is it possible to call calculate without writing the instructions again? You do notcalla process. The process above issensitiveon A, B and C. > is it possible in an architecture to call a process several times only > by changing its variables ?! These aren'tvariablesbutsignals! But for this here:

1 | calculate:process(A,B,C) |

2 | ```
begin
``` |

3 | C<=A+B; |

4 | end process calculate; |

you do not need a process at all. Write it down this way:

1 | C<=A+B; |

Thats the concurrent style.

u didnt realy answer my question, i know A B and C are signals, u said i need a function , so how can i write this and call it for D E and F ?! thank you

> u didnt realy answer my question Because the question itself doen't make much sense... In the process calculate: process(A,B,C) the Symbols A, B, and C are not parameters that are handed over to the process. The are just flags, which say to recalculate the process on every change of each of them. > i need a function , so how can i write this

1 | function calculate (da : std_logic_vector, db : std_logic_vector) |

2 | return std_logic_vector is |

3 | variable t : std_logic_vector := '0'; |

4 | ```
begin
``` |

5 | t := da + db; -- higly dependent on libraries |

6 | return t; |

7 | end calculate ; |

8 | ```
:
``` |

9 | ```
:
``` |

10 | c <= calculate(a,b); |

11 | f <= calculate(d,e); |

But what about typing in the words function+vhdl into google? On the other hand duplicating ressources can be done with ageneratestatement or aloop.

regarding functions in VHDL: keep in mind that the output of synthesis tools has to be watched carefully if you use high-level vhdl constructs like functions... the output may in some cases be not very effective or not of that kind as you expected