# Forum: FPGA, VHDL & Verilog Fraction sfixed

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Dear All,

In our calculations we have a sfilxed value:

SIGNAL Bin : sfixed(9 DOWNTO -9); -- ( = 2.7 )

Now I want to have the fractional part as integer (=7) in a signal and
the "integer" part (=2) in another signal.

How can I do this? Is there an example?

I'm not succeeding even when using the round_style or overflow_style
options.

With kind regards,

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> Now I want to have the fractional part as integer (=7) in a signal
Thats not the way the type sfixed ist working!!

The bits are weighted:
 1 sfixed(9 DOWNTO -9) :  2  9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9  3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 
And now 2.7 is
 1  9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9  2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2  3 =  4 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 
So you can easily see: the first 10 bits are simply:
0000000010 = 2

But the fraction is far far away from anything looking like 7:
101100110
In fact its not .7 but .69916875, the nearest representable number :-o

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Dear Na sowas,

Thank you very much for your quick reaction.

That's just my problem. I need the 7 (or 69916875) in a signal but I
don't know how to extract it from the sfixed.

I hope you can tell me how.

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Lets get a step further:
Given the number 2.7 you want as result the numbers 2 and 7?
What do you want for 2.76? Or for 2.765 or 2.7654?

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> Given the number 2.7 you want as result the numbers 2 and 7?

Yes, that's right.

> What do you want for 2.76? Or for 2.765 or 2.7654?

A fixed number of digits lets say 3 (rounded):

for example in this case (skipping the signal "2"):

2.7     ->  "700"
2.76    ->  "760"
2.765   ->  "765"
2.7654  ->  "765"

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