Hi,
I am having trouble finding the reason for a hard fault exception on my
cortex-M3 (STM32F107). I have implemented the exception handler
according to the book "The definiteve guide to the ARM Cortex-M3".
The assembler part:
From this I can see that in CFSR's BFSR part bit bit 2 (IMPRECISERR) is
set. According to the book this means:
"Bus error during data access. Bus error could be caused by device not
being initialized, access of privileged-only device in user mode, or the
transfer size is incorrect for the specific device."
I was also able to find the source code line that causes the exception:
Register sp conatains 0x200010f4 (before executing the LDRB
instruction), which is in the RAM area.
Any ideas on what's going wrong here?
Thanks in advance for your tips and help!
P.S.: I am using the RealView compiler.
--
Regards,
Marco
No.
LDR r1,[pc,#296] ; @0x08000880
loads the address of devData from the constant pool
LDR r1,[r1,r4,LSL #2]
loads devData[minorNum]
STR r0,[r1,#0x04]
devData[minorNum]->writeMutex = ...
Correct so far. But we lack information about R4=minorNum. Most likely
the STR instruction fails because the address loaded in the 2nd LDR is
invalid (0).
Marco ... wrote:> r0 = 0x20001174> r1 = 0x00000000>> RAM starts at 0x20000000 and is 64 KB long.>> So that assembler instruction should store 0 to RAM area.
No. It stores 0x20001174 to 0x4.
A. K. wrote:
[...]
> Correct so far. But we lack information about R4=minorNum. Most likely> the STR instruction fails because the address loaded in the 2nd LDR is> invalid (0).
r4 = 0 before executing
Thanks to your hints, I found the trace to follow and solved the problem
now.
--> Dangling pointer for devData...
Many thanks for your help!
--
Regards,
Marco
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