Hi I am doing a project with a fifo in VHDL. Specifically I am trying to send 1024 bytes of data at a time through the fifo (and over ethernet). My input data width is 32 bits and my output data width is 8 bits. When hardwaring my write enable signal to a constant high and controlling when the fifo reads out data (when it has 1024 bytes of data), it seems to work fine. However, I am trying to use a square wave for the write enable signal and when I do this, the fifo outputs data for a short period of time and then stops. When trying to debug this problem I looked at the prog_full flag, write enable flag, empty flag, write acknowledge flag, and the write data count. The result is that it seems the write data count stays at a constant value of 14 ("00000001110"). the write acknowledge signal is low which indicates the write command was unsuccessful. However the write enable signal is a square wave as expected. Does anyone know whats going on? Thanks in Advance. Andy
> with a fifo in VHDL
What architecture/toolchain?
Is this behaviour in simulation or in real hardware?
Wheres the fifo from? Self written or a fifo core?
It is a Xilinx board with a Virtex 5 FPGA This behavior is in real hardware the fifo is a fifo core (known as Fifo Generator by a company known as LogiCORE)
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