Forum: ARM programming with GCC/GNU tools System Bus Interface in S3C2440

von Sandeep G. (grsandeep85)

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Hi All,

          I am using Samsung S3C2440 board to which linux kernel is 
ported and now i have an application board i need to make the system bus 
interface for my application board and S3C2440 board(i.e., memory 
mapping of Address and Data bus of S3C2440 to Address and Data bus of 
application board). How to do this.. any suggestions please.

von Clifford S. (clifford)

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Your question is somewhat short of essential detail.  The term 
"application board" is rather vague.

Either way you probably need to familiarise your self with Chapter 5 - 
Memory Controller of the S3C2440 User Manual.  There are 8 banks each of 
which select a 128Mb address space, all banks support conventional ROM, 
SRAM type address/data bus, and two additionally support SDRAM. All 
banks support 8/16/23 bit data bus, except Bank 0 which has only 16/32 
bit bus support. One of these banks will already be used by your board 
for SDRAM, and another for Flash memory.  Possibly there are additional 
memory mapped devices on your board, which may use additional bank slect 
lines.  Your board's user guide or schematic will tell you which ones 
are available.  Basically you need to hook up your board to the 
necessary data and address lines, and the bank select to the data bus 
tri-state latch (chip select), and hook up the R/W select line.

You will also need to enable the selected memory region in the MMU 

von Sandeep G. (grsandeep85)

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     Thanks for your reply i have attached the application board 
schematic here i mapped the address bus (A1-A3) and Data bus (D0-D7)to 
IDE connector of address bus (LADDR1-LADDR3) and data bus 
(LDATA0-LDATA7). Also i have made a code the if i select the particular 
memory location say 0x08000000 then the chip select(nGCS1) has to enable 
and if i continuously read the content of the memory location then the 
chip select(nGCS1) has to enable continuously till i kill the execution 
of the program. If i check the nGCS1 pin of the IDE connector in the CRO 
chip select will happens only once but not continuously. Please find the 
attachment and below code.

#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <sys/ioctl.h>

#define MAP_SIZE 4096UL    
#define MAP_MASK (MAP_SIZE - 1)  

#define DATA      0x08000000 

int main(int argc, char *argv[]) {
    int fd;
    void *map_base, *virt_addr; 
    unsigned long read_result, writeval;

    if((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1)
  return -1;
    map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, DATA & ~MAP_MASK);
    if(map_base == (void *) -1)
  return -1;
    virt_addr = map_base + (DATA & MAP_MASK);
    read_result = *((unsigned long *) virt_addr);

    // Write into the memory location 0x08000000
    writeval = read_result;
    writeval = 0x0AA; //WRITE THE DATA TO MEMORY
    *((unsigned long *) virt_addr) = writeval;
    printf("writeval = 0x%X\n", writeval);

    //Read the content of the memory location 0x08000000
    read_result = *((unsigned long *) virt_addr);
    printf("read_result = 0x%X\n",read_result);

    if(munmap(map_base, MAP_SIZE) == -1)
  return -1;

    return 0;


von Clifford S. (clifford)

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I am no expert on Linux, but you will at least need to disable the cache 
for the application board's memory mapped region, otherwise you will 
simply read what is in the cache rather than what is on the board - 
which might explain the apparent single access.

Similarly you should declare pointers that map to the region as 
volatile; otherwise the optimiser may potentially remove a read and use 
the value previously read into a register.


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