VHDL records

Mark G. OP (Company: JHU Applied Physics Lab) #1580627
Rate this post
• ▲ useful
▼ not useful 
I am trying to figure out if it is possible to assign all contents of a 
record with a single statement or assign an output port as the entirety 
of a record...for example:

Declarations & signal creation...etc...
1
type MY_RECORD is record

2
    A : std_logic;

3
    B : std_logic;

4
    C : std_logic_vector(5 downto 0);

5
    D : std_logic_vector(8 downto 0);

6
    E : std_logic_vector(14 downto 0);

7
  end record;

8


9
signal my_new_rec : MY_RECORD;

1
 process (SYSCLK, nRESET) is

2
  begin

3
    if nRESET = '0' then

4
      my_new_rec  <= (others => '0');

5
 ...

6
...

7
PORT_OUT  <= my_new_rec;


I've tried the .ALL (e.g. my_new_rec.ALL) but that is of course used 
with variables.  Then I began to wonder if it might be possible to 
complete this task by using variables as an intermediate?  If anyone has 
any ideas please let me know.  In short, I'm trying to use records to 
further subdivide a 32 bit std_logic_vector so I can do things like:

1
if(my_new_rec.A = '1') then

2
etc...

3
end if;


Please help.

  





  

    Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
  








      

      



  

    

      Duke Scarring

    

      Guest


    

    
    #1580653
  




  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
With a default constant like this:
1
type MY_RECORD_t is record

2
    A : std_logic;

3
    B : std_logic;

4
    C : std_logic_vector(5 downto 0);

5
    D : std_logic_vector(8 downto 0);

6
    E : std_logic_vector(14 downto 0);

7
end record;

8
constant default_my_record_c : my_record_t := (

9
  a => '0',

10
  b => '0',

11
  c => (others => '0'),

12
  d => (others => '0'),

13
  e => (others => '0')

14
);

15


16
signal my_new_rec : MY_RECORD_t;

1
 process (SYSCLK, nRESET) is

2
  begin

3
    if nRESET = '0' then

4
      my_new_rec  <= default_my_record_c;

5
 ...

6
...

7
PORT_OUT  <= my_new_rec;


Duke

  





  

    Reply Quote Edit Delete Report post
  








      

      





      

      



  

    

      Mark G.
      

    OP


      (Company: JHU Applied Physics Lab)

    

    
    #1580758
  




  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Duke, I think your method is a good solution to initialize a 
record...thanks!
Andreas, I think this is one possible solution to parsing individual 
parts of a vector...but in my scenario I will have tens of these records 
of different types and I'm concerned these aliases could take up alot of 
code space.  I think what I've found is that records are not the answer 
to my problem.

To follow up, what are your suggestions to taking an input 
std_logic_vector(31 downto 0) and also an output std_logic_vector(31 
downto 0) and having the ability to dynamically "cast" these to 
particular "formats" based on a given state.  In other words, maybe at a 
given time each bit in the input std_logic_vector has a different 
"name", but in another state the input is divided into an upper and 
lower word.  instead of doing:

1
alias a is input(0);

2
alias b is input(1);

3
alias c is input(2);

4
...

5


6
alias a_a is input(31 downto 16);

7
alias a_b is input(15 downto 0);

8
...


I would have tens and tens if not hundreds of aliases if I did it this 
way, which is why I tried using records until I found out there 
limitations.  No other solutions?

  





  

    Reply Quote Edit Delete Report post
  









    

    

       Watch this topic


    

        


Reply




  
Please log in before posting.

  

  
Existing account



  

    

      

        
        
      

      

        
        
      

    


    

      
      
    




  
or

  Log in with Google account





  
No account?

  
Registration is free and takes only a minute.

  Register now