Forum: FPGA, VHDL & Verilog VHDL records

 Author: Mark G. (Company: JHU Applied Physics Lab) (mwgilson) Posted on: 2010-02-02 15:16

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I am trying to figure out if it is possible to assign all contents of a
record with a single statement or assign an output port as the entirety
of a record...for example:

Declarations & signal creation...etc...
 type MY_RECORD is record A : std_logic; B : std_logic; C : std_logic_vector(5 downto 0); D : std_logic_vector(8 downto 0); E : std_logic_vector(14 downto 0); end record; signal my_new_rec : MY_RECORD; 
  process (SYSCLK, nRESET) is begin if nRESET = '0' then my_new_rec <= (others => '0'); ... ... PORT_OUT <= my_new_rec; 

I've tried the .ALL (e.g. my_new_rec.ALL) but that is of course used
with variables.  Then I began to wonder if it might be possible to
complete this task by using variables as an intermediate?  If anyone has
any ideas please let me know.  In short, I'm trying to use records to
further subdivide a 32 bit std_logic_vector so I can do things like:

 if(my_new_rec.A = '1') then etc... end if; 

Please help.

 Author: Duke Scarring (Guest) Posted on: 2010-02-02 15:30

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With a default constant like this:
 type MY_RECORD_t is record A : std_logic; B : std_logic; C : std_logic_vector(5 downto 0); D : std_logic_vector(8 downto 0); E : std_logic_vector(14 downto 0); end record; constant default_my_record_c : my_record_t := ( a => '0', b => '0', c => (others => '0'), d => (others => '0'), e => (others => '0') ); signal my_new_rec : MY_RECORD_t; 
  process (SYSCLK, nRESET) is begin if nRESET = '0' then my_new_rec <= default_my_record_c; ... ... PORT_OUT <= my_new_rec; 

Duke

 Author: Andreas S. (andreas) (Admin) Posted on: 2010-02-02 15:38

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You can't use records to directly subdivide a vector. If you want to use
a record, you need to assign the components manually (or write a
function to do it). Another option is using aliases:

 alias a is my_slv(5); alias b is my_slv(4 downto 0); if (a = '1') then ... end if; 

 Author: Mark G. (Company: JHU Applied Physics Lab) (mwgilson) Posted on: 2010-02-02 16:30

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Duke, I think your method is a good solution to initialize a
record...thanks!
Andreas, I think this is one possible solution to parsing individual
parts of a vector...but in my scenario I will have tens of these records
of different types and I'm concerned these aliases could take up alot of
code space.  I think what I've found is that records are not the answer
to my problem.

std_logic_vector(31 downto 0) and also an output std_logic_vector(31
downto 0) and having the ability to dynamically "cast" these to
particular "formats" based on a given state.  In other words, maybe at a
given time each bit in the input std_logic_vector has a different
"name", but in another state the input is divided into an upper and

 alias a is input(0); alias b is input(1); alias c is input(2); ... alias a_a is input(31 downto 16); alias a_b is input(15 downto 0); ... 

I would have tens and tens if not hundreds of aliases if I did it this
way, which is why I tried using records until I found out there
limitations.  No other solutions?

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