attributes in vhdl

Your problems seems to be very urgent, as you even couldn't find the 
time to write a readable question :-)

Anyway, some attributes are supported for sythesis and others are not.
This is not a matter of including libraries or packages.

Tell us which attributes you would like to use and somebody can tell you 
if they are suitable or not.
The attributes 'stable or 'transaction, which you mentioned in another 
thread, are for testbenches only

I have also not understand your question without code reproducer.
Perhaps you will found on this side an explaination.

http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/objects__data_types_and_operators/understanding_vhdl_attributes.htm

> not supported by xilinx
> i want to implement NMOS transister
The Xilinx toolchain is designed for Xilinx FPGAs. Its not intended for 
ASIC design. You will never be able to synthesize a single transistor 
with this tools. So of course these attributes are not supported.

The only thing you can do with your code is simulation. But for this you 
should use a stand alone simulator (eg ModelSim), not a FPGA specific 
toolchain...

> this simulation will not be supported by xilinx fpga
No simulation is supported by any FPGA.

Simulation is done in the simulator. This may be ModelSim or ISM or...
Of course in a Simulation you can use the attributes. But the only 
attribute supported for synthesis is 'EVENT for rising or falling edges 
of a clock signal.

So what do you want to do?
Do you want to target a FPGA?
Or do you "only" want to simulate your VHDL code?

> my task is both simulation and implementation !!!
Keep in mind:
>> the only attribute supported for synthesis is 'EVENT
Then forget all other attributes for synthesis.

> what will be the solution!!
You are obviuosly on a wrong way. If you want to simulate a ROM then you 
should do it like all others all over the world are doing it. This is a 
ROM:

1

type ROM_type is array(0 to 7) of STD_LOGIC_VECTOR(7 downto 0);

2

signal ROM : ROM_type := {x"12", x"23", x"34", x"45", x"56", x"67", x"78", x"89");

You access it like this:

1

signal addr : STD_LOGIC_VECTOR(3 downto 0);

2

signal data : STD_LOGIC_VECTOR(7 downto 0);

3

:

4

   data <= ROM(to_integer(unsigned(addr)));

BTW:
It looks far more friendly when you don't use lots of exclamation marks 
at the end of a sentence.

BTW2:
> what will be the solution!!
This is a question. It should look like this:
> what will be the solution?

I done underestand attribute equivalent_register_removal of 
Bus_Struct_Reset : signal is "no" .
please explain for me and convert to verilog .tanks

hi.
i dont underestand :attribute equivalent_register_removal of 
Bus_Struct_Reset : signal is "no" .
please explain for me and convert to verilog.
tanks

What do you refer to?
Where can I find the Bus_Struct_Reset and its attribute?

> equivalent_register_removal
Try this:
http://lmgtfy.com/?q=+xilinx+attribute+equivalent_register_removal

> tanks
... are used in wars to destroy parts of the opponent army  :-o

> please explain fo me and convert to verilog .
This is done there:
http://lmgtfy.com/?q=+xilinx+attribute+equivalent_register_removal
So why should someone do the same work a second time?

> I have not time.
What the he*%&$³##!&=?
You don't have time, so I should spend mine?