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Forum: ARM programming with GCC/GNU tools LPC2103 - UART0 Interrupt Problem


von Jongmun K. (Company: inno) (jmkim519)


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Dear all,

I am Using LPC2103, I had Configured UART0 to IRQ

When working, VIC Register Status is
 -------------------------------------------
  vicIntSelect = 0;
  vicIntEnable = 0x000040;
  vicIRQStatus = 00000040;

  vicVectCtrl0 = 0x000026;
  vicVectAddr0 = 0x000380;
  vicVectAddr  = 0x000380;
 -------------------------------------------

But Didn't happen to uart0_rx_isr Routine

Could some body help me regarding this.


 -------------------------------------------
          /* Exception Vector Table */

_vectors:       ldr     PC, Reset_Addr
                ldr     PC, Undef_Addr
                ldr     PC, SWI_Addr
                ldr     PC, PAbt_Addr
                ldr     PC, DAbt_Addr
                nop
                ldr     PC, [PC,#-0xFF0]
                ldr     PC, FIQ_Addr

 -------------------------------------------
           /* My Working Code */

#include "LPC210x.h"

void uart0_rx_isr(void);

int main()
{
        PINSEL0 &= (~(0xF) & 0xFFFFFFFF);
        PINSEL0 |= 0x5;

        UART0_FCR = 0x7;
        UART0_LCR = 0x83;
        UART0_DLL = 0x41;

        UART0_DLM = 0x0;
        UART0_LCR = 0x3;

        /* Setting Interrupt */
        UART0_IER = 0x3;
        VICIntEnClr     = 0xFFFFFFF0;
        VICIntSelect    = 0x00000000;
        VICVectCntl0    = ((0x1<<5) | 6);
        VICVectAddr0    = (unsigned long)uart0_rx_isr;

        VICIntEnable    = (1<<6);
}

void uart0_rx_isr(void)
{
        volatile unsigned long uart0IIR = 0;

        uart0IIR = UART0_IIR;

        while (!(UART0_LSR & 1<<5));
        UART0_THR = 'T';

        VICVectAddr = 0;
}

von (prx) A. K. (prx)


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Is the processor interrupt enabled? ARM7 startup codes often call main() 
with interrupts disabled and your main enables the interrupts in VIC but 
not in the processor. Also it is rather undefined what happens once 
main() terminates.

BTW: A local variable of an interrupt handler almost never has to be 
"volatile". Only vars which could be accessed outside of the compilers 
visibility have to be volatile (such as a main program's var accessed by 
an interrupt handler).

von Jongmun K. (Company: inno) (jmkim519)


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Thx. For your help.
But I am a beginner, I don't know exactly.
Here My startup code, For processor interrupt Enable, what I have to do?
1
/* Stack Sizes */
2
.set  UND_STACK_SIZE, 0x00000004    /* stack for "undefined instruction" interrupts is 4 bytes  */
3
.set  ABT_STACK_SIZE, 0x00000004    /* stack for "abort" interrupts is 4 bytes                  */
4
.set  FIQ_STACK_SIZE, 0x00000004    /* stack for "FIQ" interrupts  is 4 bytes               */
5
.set  IRQ_STACK_SIZE, 0X00000004    /* stack for "IRQ" normal interrupts is 4 bytes          */
6
.set  SVC_STACK_SIZE, 0x00000004    /* stack for "SVC" supervisor mode is 4 bytes          */
7
8
9
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/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs (program status registers) */
11
.set  MODE_USR, 0x10                /* Normal User Mode                     */
12
.set  MODE_FIQ, 0x11                /* FIQ Processing Fast Interrupts Mode             */
13
.set  MODE_IRQ, 0x12                /* IRQ Processing Standard Interrupts Mode           */
14
.set  MODE_SVC, 0x13                /* Supervisor Processing Software Interrupts Mode       */
15
.set  MODE_ABT, 0x17                /* Abort Processing memory Faults Mode             */
16
.set  MODE_UND, 0x1B                /* Undefined Processing Undefined Instructions Mode     */
17
.set  MODE_SYS, 0x1F                /* System Running Priviledged Operating System Tasks  Mode  */
18
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.set  I_BIT, 0x80                   /* when I bit is set, IRQ is disabled (program status registers) */
20
.set  F_BIT, 0x40                   /* when F bit is set, FIQ is disabled (program status registers) */
21
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.text
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.arm
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.global  Reset_Handler
27
.global _startup
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.func   _startup
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_startup:
31
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# Exception Vectors
33
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_vectors:       ldr     PC, Reset_Addr
35
                ldr     PC, Undef_Addr
36
                ldr     PC, SWI_Addr
37
                ldr     PC, PAbt_Addr
38
                ldr     PC, DAbt_Addr
39
                nop              /* Reserved Vector (holds Philips ISP checksum) */
40
                ldr     PC, [PC,#-0xFF0]  /* see page 71 of "Insiders Guide to the Philips ARM7-Based Microcontrollers" by Trevor Martin  */
41
                ldr     PC, FIQ_Addr
42
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Reset_Addr:     .word   Reset_Handler    /* defined in this module below  */
44
Undef_Addr:     .word   UNDEF_Routine    /* defined in main.c  */
45
SWI_Addr:       .word   SWI_Routine      /* defined in main.c  */
46
PAbt_Addr:      .word   UNDEF_Routine    /* defined in main.c  */
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DAbt_Addr:      .word   UNDEF_Routine    /* defined in main.c  */
48
IRQ_Addr:       .word   IRQ_Routine      /* defined in main.c  */
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FIQ_Addr:       .word   FIQ_Routine      /* defined in main.c  */
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                .word   0          /* rounds the vectors and ISR addresses to 64 bytes total  */
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# Reset Handler
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Reset_Handler:
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        /* Setup a stack for each mode - note that this only sets up a usable stack
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        for User mode.   Also each mode is setup with interrupts initially disabled. */
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          ldr   r0, =_stack_end
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          msr   CPSR_c, #MODE_UND|I_BIT|F_BIT   /* Undefined Instruction Mode  */
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          mov   sp, r0
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          sub   r0, r0, #UND_STACK_SIZE
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          msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT   /* Abort Mode */
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          mov   sp, r0
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          sub   r0, r0, #ABT_STACK_SIZE
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          msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT   /* FIQ Mode */
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          mov   sp, r0
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           sub   r0, r0, #FIQ_STACK_SIZE
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          msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT   /* IRQ Mode */
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          mov   sp, r0
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          sub   r0, r0, #IRQ_STACK_SIZE
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          msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT   /* Supervisor Mode */
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          mov   sp, r0
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          sub   r0, r0, #SVC_STACK_SIZE
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          msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT   /* User Mode */
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          mov   sp, r0
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        /* copy .data section (Copy from ROM to RAM) */
80
                ldr     R1, =_etext
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                ldr     R2, =_data
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                ldr     R3, =_edata
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1:            cmp     R2, R3
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                ldrlo   R0, [R1], #4
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                strlo   R0, [R2], #4
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                blo     1b
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        /* Clear .bss section (Zero init)  */
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                mov     R0, #0
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                ldr     R1, =_bss_start
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                ldr     R2, =_bss_end
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2:        cmp     R1, R2
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                strlo   R0, [R1], #4
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                blo     2b
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        /* Enter the C code  */
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                b       main
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.endfunc
100
.end

von Jongmun K. (Company: inno) (jmkim519)


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I figure out the problem.

When I change processor Interrupt Enable, it working.

I change Below

first, Stack size change
1
  .set  IRQ_STACK_SIZE, 0X00000004 
2
3
  -->
4
5
  .set  IRQ_STACK_SIZE, 0X00000080

second, IRQ Enable
1
  msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT   /* User Mode */
2
3
  -->
4
5
  msr   CPSR_c, #MODE_USR   /* User Mode */

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