1 | process(ps2_clk, CurrentState)
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2 | begin
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3 | NextState <= CurrentState;
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4 | case CurrentState is
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5 | when idle =>
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6 | if falling_edge(ps2_clk) then ----------------<<<
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7 | :
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8 | end if;
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9 | when receiving =>
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10 | if falling_edge(ps2_clk) then ----------------<<<
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11 | :
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12 | end if;
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13 | when transm_complete =>
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14 | if goto_idle = '1' then
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15 | NextState <= idle;
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16 | end if;
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17 | end case;
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18 | end process;
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19 | end Behavioral;
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You can try to simulate this, but you will never get it through the
synthesizer.
1 | process(ps2_clk, CurrentState)
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2 | begin
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3 | NextState <= CurrentState;
|
CurrentState is combinatorial assigned to NextState, there's no
clock or delay between. It's just the same. I don't think, thats what
you really want :-/
1 | :
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2 | CurrentState <= NextState; -------------------<<<
|
3 | end if;
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4 | end if;
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5 | end process;
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6 |
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7 | process(ps2_clk, CurrentState)
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8 | begin
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9 | NextState <= CurrentState; --------------------<<<
|
10 | :
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Hmmm...
This looks much like a infinte loop.
> It is now working!
Believe me:
You're much farther away from your destination than you may think :-o
You're not the first one to interface a keyboard to a FPGA, so have a
look around how others are doing the job ;-)