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Forum: FPGA, VHDL & Verilog PS/2 Interface


von Martin (Guest)


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Hi, as part of an assignment I have to write a PS/2 interface. Here's 
the code that I've written so far:
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ps2_if is
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  port(
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    clk, rst : IN std_logic;
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    ps2_clk : IN std_logic;
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    ps2_dat : IN std_logic;
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    data_out : OUT std_logic_vector(7 downto 0);
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    valid_out : OUT std_logic
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  );
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end ps2_if;
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architecture Behavioral of ps2_if is
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  type State is (idle, receiving, transm_complete);
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  signal CurrentState, NextState : State;
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  signal goto_idle : std_logic;
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  signal i : integer range 0 to 9 := 9;
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  signal data : std_logic;
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begin
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  process(clk, rst)
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  begin
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    if rising_edge(clk) then
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      if rst = '1' then
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        data_out <= (others => '0');
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        valid_out <= '0';
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      else
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        if CurrentState = transm_complete then
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          valid_out <= '1';
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          goto_idle <= '1';
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        elsif CurrentState = idle then
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          valid_out <= '0';
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          goto_idle <= '0';
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        end if;
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        CurrentState <= NextState;
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      end if;
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    end if;
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  end process;
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  process(ps2_clk, CurrentState)
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  begin
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    NextState <= CurrentState;
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    case CurrentState is
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      when idle =>
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        if falling_edge(ps2_clk) then
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          NextState <= receiving;
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          i <= i-1;
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        end if;
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      when receiving =>
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        if falling_edge(ps2_clk) then
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          if i = 0 then
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            NextState <= transm_complete;
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            i <= 7;
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          else
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            data_out(i-1) <= ps2_dat;      
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            i <= i-1;
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          end if;
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        end if;
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      when transm_complete =>
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        if goto_idle = '1' then
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          NextState <= idle;
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        end if;
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    end case;
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  end process;
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end Behavioral;

The problem I don't really know how to solve is: even though the code 
seems to be correct to me the simulator wouldn't the data from ps2_dat 
to the data_out vector. As I don't know VHDL well, I'm struggling to 
find the mistake.
I'm using the Xilinx Web Pack, v11.1 with the built-in simulator.
Does anybody see what the problem is?
Thanks a lot in advance!
Martin

von waxology (Guest)


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you couldn´t assign signals values in different processes!!
1
data_out <= (others => '0');
in the process above and
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data_out(i-1) <= ps2_dat;
so both process will work parallel and data_out will probably be 'X'?
A simple structure to describe processe in vhdl is
[vhdl]
XXX: process(CLK, NRES)
begin
  if (NRES = '0') then
    ...
  elsif (rising/falling_edge(CLK) then
    ...
  end if;
end process

von Martin (Guest)


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Hi waxology,
thanks a lot. It is now working! The command
1
data_out <= (others => '0');
really seems to have been the problem. But when I remove it the vector 
won't be reset on a rst event. Could you tell me how to get that right?
Another problem I noticed now is that valid_out which is supposed to be 
1 for one clock cycle when all the bits have arrived only goes back to 0 
after three cylces (clk cicles). Do you have any idea, why?
Martin

von Lothar M. (lkmiller) (Moderator)


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1
  process(ps2_clk, CurrentState)
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  begin
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    NextState <= CurrentState;
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    case CurrentState is
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      when idle =>
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        if falling_edge(ps2_clk) then   ----------------<<<
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        :
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        end if;
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      when receiving =>
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        if falling_edge(ps2_clk) then   ----------------<<<
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        :
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        end if;
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      when transm_complete =>
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        if goto_idle = '1' then
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          NextState <= idle;
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        end if;
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    end case;
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  end process;
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end Behavioral;
You can try to simulate this, but you will never get it through the 
synthesizer.


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  process(ps2_clk, CurrentState)
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  begin
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    NextState <= CurrentState;
CurrentState is combinatorial assigned to NextState, there's no 
clock or delay between. It's just the same. I don't think, thats what 
you really want  :-/


1
        :
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        CurrentState <= NextState; -------------------<<<
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      end if;
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    end if;
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  end process;
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  process(ps2_clk, CurrentState)
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  begin
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    NextState <= CurrentState;   --------------------<<<
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    :
Hmmm...
This looks much like a infinte loop.



> It is now working!
Believe me:
You're much farther away from your destination than you may think  :-o
You're not the first one to interface a keyboard to a FPGA, so have a 
look around how others are doing the job  ;-)

von Martin (Guest)


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Hello Lothar Miller,
thanks for the reply. I modified the first part you mentioned e.g. 
replacing the
1
if falling_edge(ps2_clk)...
parts by one right at the beginning of the process. Concerning the 
signals of the FSM I also modified the code. And well, it passed the 
synthesizer.
I think the main problem I have is that I have difficulties thinking in 
the hardware design way. That's why some parts of the code are somewhat 
strange.

von René D. (Company: www.dossmatik.de) (dose)


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You have to read

FPGA Prototyping by VHDL Examples written by Pong p.Chu

There are inside a PS2 interface example.

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