VHDL & string conversion

Guest #1187615
Hello embdev-Community.

I'm from Germany, but I'll do my very best in writing clean English ;)

I am developing with VHDL since a few weeks, I love this method to 
design hardware. All this time along I used the Xilinx ISE to create 
testbenches for evaluation.

But today I decided to write my own bench on a linuxbox. This was a 
little difficult, but in the end it worked.

I coded a for loop which iterates an array of pattern and stimulates my 
entity with the desired values. After that it compares the output saved 
in the array with the output of the entity.

If this doesn't match, an error-string is shown.

But I want to tweak this a little bit. It is not really helpful to see, 
that an error occures. It would be great to see, on which index of the 
pattern-array this thing happened.

But I really don't know how to convert the iterator i:
1
for i in pattern'range loop
to a string in my error string.

My actual output is:
1
assert Q_is = patterns(i).Q
2
report "Q doesn't match!" severity error;

But I want something like: "Q doesn't match @ i", where i is replaced by 
it's value.

Since I only coded CPLD-Hardware for synthesizing, I'm absolutely 
unfamiliar with strings a.s.o. in VHDL.

Hope, someone could help.

Greets and best wishes from Germany,
Sebastian
Guest
Herzlichsten Dank, genau das hat mir gefehlt!

Gibt es eine Übersicht solcher Debug und Testing Anweisungen?

Grüße,
Sebastian
Guest
Sorry, I wrote back in the german board, didn't mind that my post will 
appear also in the english.

I asked about a kind of list or summary with the most used debugging- 
and testing-codes in VHDL.

Greets, Sebastian

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