I am trying to store byte arrays in SDRAM, but byte write accesses swap
byte order.
If anybody knows what to do in order to eliminate this byte swapping, I
will appreciate help.

This is a simple code that should work well but is working wrong:

//array is stored in SDRAM
uint8_t array[4];

array[0] = 0xAA;
array[1] = 0xBB;
array[2] = 0xCC;
array[3] = 0xDD;

for(i=0;i<4;i++)
{
    print_hex(array[i]);
}

...and the output will be: BB AA DD CC
instead of expected:       AA BB CC DD

As you see, bytes are swapped within each half-word read back from
SDRAM.
The same happens when I use PDC writes (for example byte-after-byte
transfers from UART) - bytes in halfwords are swapped too.

When I write half-words or words to SDRAM, I read back bytes in expected
order
uint32_t aVariable = 0xDDCCBBAA;
uint8_t *ptr = (uint8_t*)&aVariable;
for(i=0;i<4;i++)
{
    print_hex(ptr[i]);
}
...the output will be as expected AA BB CC DD

Byte swapping effect doesn't appear when array was placed in internal
SRAM.
16-bit half-word and 32-bit word accesses (writes and reads) to SDRAM
are totally OK and symmetrical.
I run program form SDRAM, so probably SDRAM config is OK.
Byte swapping appears even when I slowed down the MCK clock from ~100MHz
to ~50MHz

This is my hardware configuration:

MCU: AT91SAM9260
SDRAM chip: Samsung K4S280432 (8Mx16)
Board: 2-layer, my design, all VDDs decoupled with 100n, lines are as
short as possible (SDRAM under the MCU)
SDRAM config: 1 chip, 16-bit data bus, connections exactly as in
AT91SAM9260 datasheet (1-chip 16-bit option)
MCU --- SDRAM
D15-D0  D15-D0
A0      DQML
A2-11   A0-A9
SDA10   A10
BA0     BA0
BA1     BA1
SDCKE   SDCKE
SDCK    SDCK
NBS1    DQMH
RAS     RAS
CAS     CAS
SDWE    WE
SDCS_NCS1 CS

My SDRAM CR init is:
AT91C_BASE_SDRAMC->SDRAMC_CR =
AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_12
| AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS
| AT91C_SDRAMC_DBW_16_BITS
| AT91C_SDRAMC_TWR_2
| AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2
| AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5
| AT91C_SDRAMC_TXSR_8;

rest of the config is the same as in SDRAM appnote

Regards,
Robert