Amit Chatre wrote:

>//OT is time out in seconds TimeOut i incremented in ISR Routine
volatile?

There should be some index-checking before doing this:
>           gArr[gRn-1][gCn]=0;
and this
>           gArr[gRn-1][gCn]=gData;
and this
>           gArr[gRn-1][gCn]=gData;


>   disable_timer1();
Implementation?

Is a default interrupt-handler implemented and configured in the VIC?

Martin Thomas wrote:
> Amit Chatre wrote:
>
>>//OT is time out in seconds TimeOut i incremented in ISR Routine
> volatile?
 They were not volatile, ok I'll do that.

>
This code is working well but it not includes the timeout functinality.
before calling this function we have to set these parameters

//gRcount=3; no of response expected
//gRn=0; row count
//gCn=0; colomn count

void rDataWt(void)
{
  int gData=0;

  while(1)
  {
    if(( gData = uart1Getch() ) >= 0)
    {
      if((gData == '\r') || (gData == '\n'))
      {
        gFlag=0;
        if(gRcount == gRn)
        {
          gCn++;
          gArr[gRn-1][gCn]=0;
          break;
        }
      }else
      {
        if(gFlag == 0)
        {
          gFlag = 1;
          gRn++;
          gCn=0;
          gArr[gRn-1][gCn]=gData;
        }else
        {
          if(gFlag == 1)
          {
            gCn++;
            gArr[gRn-1][gCn]=gData;
          }
        }
      }
    }
  }
}

> There should be some index-checking before doing this:
>>           gArr[gRn-1][gCn]=0;
> and this
>>           gArr[gRn-1][gCn]=gData;
> and this
>>           gArr[gRn-1][gCn]=gData;
>
>

>>   disable_timer1();
> Implementation?
>
void initTimer1(void)
{
  T1TCR = TCR_RESET;           // reset & disable timer 1
  T1PR = T0_PCLK_DIV - 1;     // set the prescale divider
  T1MR0 = ONE_SEC;
  T1MCR = 3;                   // disable match registers
//  T1TCR = TCR_ENABLE;          // enable timer 1
}

void enable_timer1(void)
{
  T1TCR = 0x01;
}
void disable_timer1(void)
{
  T1TCR = 0x02;
}
void timer1_ISR_Setup(void)
{
  VICIntSelect &= ~VIC_BIT(VIC_TIMER1);  // UART1 selected as IRQ
  VICIntEnable = VIC_BIT(VIC_TIMER1);    // UART1 interrupt enabled
  VICVectCntl3 = VIC_ENABLE | VIC_TIMER1;
  VICVectAddr3 = (uint32_t)tc1_isr;    // address of the ISR
}
void tc1_isr(void)
{
    ISR_ENTRY();
    T1IR = 0xFF;
    Timer1_IntFlag = 0x01;
    TimeOut++;
    VICSoftIntClear = VIC_BIT(VIC_TIMER1);
    VICVectAddr = 0x00000000;
    ISR_EXIT();
}

> Is a default interrupt-handler implemented and configured in the VIC?
No I have not implimented a default interrupt-handler,
 I dont have any idea about that so please tell me how to
impliment,configure default interrupt-handler.

Amit Chatre wrote:
> Martin Thomas wrote:
>> Amit Chatre wrote:
>>
>>>//OT is time out in seconds TimeOut i incremented in ISR Routine
>> volatile?
>  They were not volatile, ok I'll do that.

And read a good C-book to understand why it should be volatile. There
are also some articels on embedded.com which explain this.

>void tc1_isr(void)
>{
>    ISR_ENTRY();
>[...]
>   VICSoftIntClear = VIC_BIT(VIC_TIMER1); // why?
>[...]
>    ISR_EXIT();
>}

How is tc1_isr declared (with nacked attribut)? Show the definition of
the macros ISR_ENTRY()/_EXIT(). Is a IRQ-wrapper assembler-code used?

>> Is a default interrupt-handler implemented and configured in the VIC?
> No I have not implimented a default interrupt-handler,
>  I dont have any idea about that so please tell me how to
> impliment,configure default interrupt-handler.

Read NXP application-note AN10414.

You may try this (not the best solution but worth a test):

// somewhere in startup before any IRQ is configured in the VIC:
   VICDefVectAddr=(uint32_t)default_handler;

// handler:
void default_handler(void) __attribute__((naked));
void default_handler(void)
{
    ISR_ENTRY();
#if 1
    T1IR = ( 1UL << 0);
    VICVectAddr = 0x00000000;
#endif
    ISR_EXIT();
}

Martin Thomas wrote:
> Amit Chatre wrote:
>> Martin Thomas wrote:
>>> Amit Chatre wrote:
>>>
>>>>//OT is time out in seconds TimeOut i incremented in ISR Routine
>>> volatile?
>>  They were not volatile, ok I'll do that.
>
> And read a good C-book to understand why it should be volatile. There
> are also some articels on embedded.com which explain this.
>
>>void tc1_isr(void)
>>{
>>    ISR_ENTRY();
>>[...]
>>   VICSoftIntClear = VIC_BIT(VIC_TIMER1); // why?
>>[...]
>>    ISR_EXIT();
>>}
>
> How is tc1_isr declared (with nacked attribut)? Show the definition of
> the macros ISR_ENTRY()/_EXIT(). Is a IRQ-wrapper assembler-code used?
>
 In this way i decleared a interrupt isr routine.
 void tc1_isr(void) __attribute__((naked));

 Yes, this is code for Entry and Exit for ISR.

#define ISR_ENTRY() asm volatile(" sub   lr, lr,#4\n" \
                                 " stmfd sp!,{r0-r12,lr}\n" \
                                 " mrs   r1, spsr\n" \
                                 " stmfd sp!,{r1}")

#define ISR_EXIT()  asm volatile(" ldmfd sp!,{r1}\n" \
                                 " msr   spsr_c,r1\n" \
                                 " ldmfd sp!,{r0-r12,pc}^")


>>> Is a default interrupt-handler implemented and configured in the VIC?
>> No I have not implimented a default interrupt-handler,
>>  I dont have any idea about that so please tell me how to
>> impliment,configure default interrupt-handler.
>
> Read NXP application-note AN10414.
>
> You may try this (not the best solution but worth a test):
>
> // somewhere in startup before any IRQ is configured in the VIC:
>    VICDefVectAddr=(uint32_t)default_handler;
>
> // handler:
> void default_handler(void) __attribute__((naked));
> void default_handler(void)
> {
>     ISR_ENTRY();
> #if 1
>     T1IR = ( 1UL << 0);
>     VICVectAddr = 0x00000000;
> #endif
>     ISR_EXIT();
> }

Ok I'll try this