Hello all,

I have been working with the new /01 rev LPC2119.  While it has
corrected a number of erratas from the earlier 'B' rev, it appears it
may have another one not yet accounted for in the current /01 errata
sheet.

I have setup a CAN TX/RX test between the two on-chip CAN controllers.
One is sending odd-ID STD messages and the other is sending even-ID EXT
messages.  After each transmission, the ID count is advanced by two
(maintaining odd or even ID) and the ID type is toggled from STD to EXT
and vice versa.  The effect is that the controllers will take turns
winning and losing arbitration every two TX messages.

I devised this test to verify that the earlier /B arbitration bug was
resolved and  it is.  The test works perfectly (up to and including the
1 mbps rate) so I decided to tests how the CAN controller handles bus
errors.

I injected a momentary short cirtuit and as per the data sheet, both
controllers signaled bus-off and disabled themselves.  However, unlike
the data sheet, they do not always recover after I re-enable them (clear
the MR bit).  IN fact, after three of four bus-off/recover cycles, the
CAN controllers fail to respond and I need to HW reset (either WDOG ,
POWER, or RESET) for them to come back online.

Note: I am checking the bus error counters and allowing for the 128 11
recessive bits required before the CAN controller goes back online.

I have read a similar post on this board (it was quite old), but there
was no response.  So, I'm hoping someone out there has some insights as
to this behavior and can explain to me what is happening.

Also, the data sheet is a bit vague as to what exactly gets reset and
what does not when the CAN controller goes bus off.  I need to know what
happens to the CAN configuration settings and to any pending TX or RX
interrupts so as to code accordingly.

Any insights would be appreciated.

Cheers!

Daniel Quinz, P. Eng.

Acacetus Inc.