Forum: ARM programming with GCC/GNU tools wildcards in makefile

von Dustin S. (dbrazeau)

Rate this post
0 useful
not useful
I am having a little trouble using wildcards in my make file this is
what I have:

%.obj :  %.asm
  @echo File: $*.asm
  @$(ASM) $(ASM_FLAGS) GNU_$*.asm
  @cp GNU_$*.o $(OBJ)/$*.obj
  @rm GNU_$*.o

I have two asm files File.asm and GNU_File.asm and I only want to
compile GNU_File.asm and not File.asm.  How do I do this?



Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.