A.K. wrote:
> Reset starts at 0, exceptions a few words up. In production you
> therefore need ROM at address 0. If you want to debug your program in
> RAM, you either need RAM at address 0 or you have to map the exception
> vectors to RAM.

thanks AK

can u give me more details or any Doc or link on this memory remaping i
will be thank ful to


robin

The vector table starts at address zero. This includes the reset vector,
which is where code starts executing from on power-up, so this needs to
be non-volatile. If you need to be able to change the exception and
interupt vectors at runtime, then RAM must be mapped to address zero.

The part user manual will contain all teh details for a specific
controller. ARM9 and StrongARM parts and later have full MMU's rather
than the simple re-mappers typically implemented on ARM7.

Clifford

More info ...

For NXP(Philips)LPC2000 series see
http://www.hitex.de/pdf/whitepapers/WP-ARM-0102.pdf

For Atmel AT91x40 see
http://www.hitex.de/pdf/whitepapers/WP-ARM-0104.pdf

Clifford

Clifford Slocombe wrote:
> More info ...
>
> For NXP(Philips)LPC2000 series see
> http://www.hitex.de/pdf/whitepapers/WP-ARM-0102.pdf
>
> For Atmel AT91x40 see
> http://www.hitex.de/pdf/whitepapers/WP-ARM-0104.pdf
>
> Clifford

Realy thanks NOW I AM CLEAR

ROBIN

Robin Singh wrote:
> Clifford Slocombe wrote:
>> More info ...
>>
>> For NXP(Philips)LPC2000 series see
>> http://www.hitex.de/pdf/whitepapers/WP-ARM-0102.pdf
>>
>> For Atmel AT91x40 see
>> http://www.hitex.de/pdf/whitepapers/WP-ARM-0104.pdf
>>
>> Clifford
>
> Realy thanks NOW I AM CLEAR
>
> ROBIN

agin small question sir :what do u mean by"change the exception and
interupt vectors at runtime",plz give ans

thanks in advance

Robin Singh wrote:
> Robin Singh wrote:
>
> agin small question sir :what do u mean by"change the exception and
> interupt vectors at runtime",plz give ans
>
> thanks in advance

When an interrupt (for example) occurs, it will execute the jump
instruction placed at the interrupt vector address. In a ROM based
static system this can be set at build time to jump to a ROM based
interrupt handler. In more complex situations it may not be possible or
convenient to have a fixed interrupt vector. For example a bootloader
may use a ROM based interrupt but loads the application to RAM which may
require different interrupt handling, so the vector must be modifiable
at run-time.

Another reason for mapping the table to RAM is that RAM is typically
faster than ROM (some LPC2xxx parts have FLASH accelerators that make
this not so in some cases), so you can reduce interrupt latency this
way. You would probably also want the handlers to execute in RAM in this
case.

Clifford

Clifford Slocombe wrote:
> Robin Singh wrote:
>> Robin Singh wrote:
>>
>>
>
>
>
> Clifford


again thank u very much sir

robin