I am trying to make systime.c work in mthomas' latest demo. systime.c is from the EFSL demo, simply adding systime.c to the makefile, including the header, and calling systime_init does not work. What happens is that the chip is reset every millisecond for about 3 seconds and then it hangs up completely. Is this the instruction that points to the FIQ function? What is going on here? Address of the FIQ function loads here? ldr r0 , [r8, #AIC_FVR] Here is a section from the startup assembly file. (where above instruction came from) .section .reset .text .global _startup .func _startup _startup: reset: /*---------------------------------------------------------------------- -------- //*- Exception vectors //*-------------------- //*- These vectors can be read at address 0 or at RAM address //*- They ABSOLUTELY requires to be in relative addresssing mode in order to //*- guarantee a valid jump. For the moment, all are just looping. //*- If an exception occurs before remap, this would result in an infinite loop. //*- To ensure if a exeption occurs before start application to infinite loop. //*--------------------------------------------------------------------- ---------*/ B InitReset /* 0x00 Reset handler */ undefvec: B undefvec /* 0x04 Undefined Instruction */ swivec: B swivec /* 0x08 Software Interrupt */ pabtvec: B pabtvec /* 0x0C Prefetch Abort */ dabtvec: B dabtvec /* 0x10 Data Abort */ rsvdvec: B rsvdvec /* 0x14 reserved */ irqvec: B IRQ_Handler_Entry /* 0x18 IRQ */ fiqvec: /* 0x1c FIQ */ /*---------------------------------------------------------------------- -------- //*- Function : FIQ_Handler_Entry //*- Treatments : FIQ Controller Interrupt Handler. //*- Called Functions : AIC_FVR[interrupt] //*--------------------------------------------------------------------- ---------*/ FIQ_Handler_Entry: /*- Switch in SVC/User Mode to allow User Stack access for C code */ /* because the FIQ is not yet acknowledged*/ /*- Save and r0 in FIQ_Register */ mov r9,r0 ldr r0 , [r8, #AIC_FVR] msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC /*- Save scratch/used registers and LR in User Stack */ stmfd sp!, { r1-r3, r12, lr} /*- Branch to the routine pointed by the AIC_FVR */ mov r14, pc bx r0 /*- Restore scratch/used registers and LR from User Stack */ ldmia sp!, { r1-r3, r12, lr} /*- Leave Interrupts disabled and switch back in FIQ mode */ msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ /*- Restore the R0 ARM_MODE_SVC register */ mov r0,r9 /*- Restore the Program Counter using the LR_fiq directly in the PC */ subs pc,lr,#4 .align 0 .RAM_TOP: .word Top_Stack Here is part of the .map file where FIQ_Handler_Entry doesnt show up, but AT91F_Default_FIQ_handler does show up. (why?) .text 0x00100000 0xe38 *Cstartup.o(.text) .text 0x00100000 0x13c Cstartup.o 0x001000bc IRQ_Handler_Entry 0x0010010c AT91F_Default_FIQ_handler 0x00100000 _startup 0x00100110 AT91F_Default_IRQ_handler 0x00100114 AT91F_Spurious_handler 0x001000b8 exit Then I went to this part of the assembly file .global AT91F_Default_FIQ_handler .func AT91F_Default_FIQ_handler AT91F_Default_FIQ_handler: b AT91F_Default_FIQ_handler .size AT91F_Default_FIQ_handler, . - AT91F_Default_FIQ_handler .endfunc I modified "b AT91F_Default_FIQ_handler" to "b systime_isr" Which is obviously the wrong thing to do because it lead me to where I am at right now. Thanks for help. -Outer_space
outer_space wrote: > I am trying to make systime.c work in mthomas' latest demo. systime.c > is from the EFSL demo, simply adding systime.c to the makefile, > including the header, and calling systime_init does not work. What > happens is that the chip is reset every millisecond for about 3 seconds > and then it hangs up completely. Sorry, but I provide a lot of example-code. Do you mean the AT91SAM-"gamma" example? The gamma-Example uses a different "approach" for handling exceptions than the AT91-efsl-Demo. In the "gamma"-Example there is a Assembler-Wrapper which is called when an INT-Exception occures. The AT91-example directly uses the Vector-Address of the AIC to branch to the ISR and in the ISR are helper-macros. This is not compatible either use a "wrapper/no macros" or no "wrapper/direct call and the macros". I have created an new EFLS-package which will be available soon. The AT91SAM example in the package is based on the "gamma"-Code and includes a modified "systime.c". Please check http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/efsl_arm/index.html today evening (GMT). > Is this the instruction that points to the FIQ function? What is going > on here? Address of the FIQ function loads here? > ldr r0 , [r8, #AIC_FVR] It seems you confuse the FIQ-Handler with the INT-Handler. > Here is a section from the startup assembly file. (where above > instruction came from) > [skip] >I modified "b AT91F_Default_FIQ_handler" to "b systime_isr" >Which is obviously the wrong thing to do because it lead me to where I >am at right now. Yes. As far is I remember the systime-Interrupt is configured as INT not FIQ. Mabye useful part from the new efsl-example (based on the AT91-"gamma"-example). Keep startup-code as is in gamma and replace the ISR in systime.c with: /*__ramfunc*/ void systime_isr(void) /* System Interrupt Handler */ { volatile unsigned long status; static int cnt; // Interrupt Acknowledge status = AT91C_BASE_PITC->PITC_PIVR; systime_value++; /* Increment Time Tick */ cnt++; if (cnt >= 500) { /* 500ms Elapsed ? */ *AT91C_PIOA_ODSR ^= LED2; /* Toggle LED2 */ cnt=0; } } Hope this helps, Martin Thomas
Hi Martin, I would like to know how to assign a timer interrupt for 50ms with AT91SAM7s64 / AT91SAM9261 MCU. Please send me if you have some info regarding this. I am using IAR EWARM version Regards Narasimha Rao my ID is snrao007@yahoo.com outer_space wrote: > >> Hope this helps, >> Martin Thomas > > > Fantastic. > > -outer_space
Narasimha Rao wrote: > I would like to know how to assign a timer interrupt for 50ms with > AT91SAM7s64 / AT91SAM9261 MCU. When using the SAM7S PIT see describtion of Register PIMR. Sorry, but the datasheet describes the needed setup better than I could here in a few words.
Martin Thomas wrote: > Narasimha Rao wrote: >> I would like to know how to assign a timer interrupt for 50ms with >> AT91SAM7s64 / AT91SAM9261 MCU. > > When using the SAM7S PIT see describtion of Register PIMR. Sorry, but > the datasheet describes the needed setup better than I could here in a > few words. Hi Martin, Thank you for the reply. I am unable to configure the FIQ interrupt for AT91SAM7s64. I followed the steps as per the datasheet like Configuring the peripherals Configure interrupt Enable Interrupt And issuing Software trigger. Still the FIQ was not invoking. What could be the reason??
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