Search results for "111"

Thread

M-Bus via Raspberry: reading out ABB B23 meter

my German post which I unfortunately cannot edit anymore. I need to read data from an ABB "B23 111-101" meter which is accessible via an IR-interface on its left side. This IR-interface is configured to M-Bus, 2400 Bd & Address 9 (arbitrary number). For reading from that IF I am using an IR Read

µC & Digital Electronics ·Moadl ·2020-04-27 12:51 ·4 Replies

File

font_rom.v

data = 8'b00000000; // 11'h10f: data = 8'b00000000; // //code x11 11'h110: data = 8'b00000000; // 11'h111: data = 8'b00000010; // * 11'h112: data = 8'b00000110; // ** 11'h113: data = 8'b00001110; // *** 11'h114: data = 8'b00011110; // **** 11'h115: data = 8'b00111110; // ***** 11'h116: data = 8'b11111110

in „text mode vga“ · FPGA, VHDL & Verilog · 2019-09-08 23:50

File

z80.lst

106: 005F 7E ld a, (hl) 107: 0060 AD xor l 108: 0061 D300 out (0), a 109: 0063 0680 ld b, 80h 110: 111: 0065 trampeln2: 112: 0065 10FE djnz $ 113: 0067 23 inc hl 114: 0068 AF xor a 115: 0069 79 ld a, c 116: 006A 17 rla 117: 006B 4F ld c, a 118: 006C D301 out (1), a 119: 006E 30EF jr nc, Loop_2inner 120

in „Hilfe bei z80 Hex Datei“ · Mikrocontroller und Digitale Elektronik · 2019-07-14 15:13

Thread

Variable clock with prescaler?

clock_out <= div(5); elsif (controlfreq <= "110") then clock_out <= div(6); elsif (controlfreq <= "111") then clock_out <= div(7); end if; end process; end bhv; [/vhdl]

<= div(5); > elsif (controlfreq <= "110") then > clock_out <= div(6); > elsif (controlfreq <= "111") then > clock_out <= div(7); I suggest to use the case-construct here. See: https://en.wikibooks.org/wiki/Programmable_Logic/VHDL_Sequential_Statement https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design

FPGA, VHDL & Verilog ·Mohamed H. ·2019-05-17 09:01 ·2 Replies

Article

Ethernet-Controller

sind aber ggf. auch als reiner Ethernet-MAC-Controller nutzbar. ( Bezugsquelle z. B.: oder SMSC LAN91C111/LAN911x/LAN921x; 10/100 MAC+PHY ASIX AX88796B; 10/100 MAC+PHY; NE2000- & RTL8019-kompatibel ASIX AX88180 10/100/1000 Ethernet MAC µC mit Ethernet-Interface. Atmel AT91SAM7X256 Atmel AT91SAMSAM9260 /

Article ·2019-03-14 07:49

Article

Soft-PWM

ändern. Das Programm ist schon um einiges länger (968 Byte). Die Interruptroutine benötigt maximal 111 Takte und wird zwischen 2 bis 9 mal pro PWM-Zyklus aufgerufen. Zweimal, wenn alle PWM-Einstellungen gleich sind, 9 mal, wenn alle PWM-Einstellungen verschieden sind. Damit werden zwischen 222 bis 999

Article ·2019-03-11 19:35

Thread

decoder in vhdl dont work in simulation.

then f<="00000100" after 1 ps; elsif a="110" then f<="00000010" after 1 ps; elsif a="111" then f<="00000001" after 1 ps; else null; end if; end if; end process; end bhv; [/vhdl]

010" after 20ns, "011" after 30ns, "100" after 40ns, "101" after 50ns, "110" after 60ns, "111" after 70ns, "000" after 80ns, "001" after 90ns, "010" after 100ns, "011" after 110ns, "100" after 120ns, "101" after 130ns, "110" after 140ns, "111" after 150ns; END; [/vhdl]

FPGA, VHDL & Verilog ·ee_vhdl ·2019-01-07 13:47 ·5 Replies

File

getval.c

; // wanted count of numbers read } #define COUNT 4 int main( void ) { char* input = "*127,255,001,111#"; uint8_t colors[COUNT]; while (true) { get_vals(input, colors, COUNT); } }

in „String parsen und zahlen Zahlen per "atoi" extrahieren klappt nicht“ · Mikrocontroller und Digitale Elektronik · 2018-12-07 13:46

File

main.c

nW: %i",color[3]); #endif // DEBUG return 0; } int main() { printf("start\n"); parse("*127,255,001,111#"); return 0; }

in „String parsen und zahlen Zahlen per "atoi" extrahieren klappt nicht“ · Mikrocontroller und Digitale Elektronik · 2018-12-04 17:29

Thread

Datapath 8 bits VHDL Modelsim

when "101" => f <= a - b; -- substact when "110" => f <= a + 1; -- increment when "111" => f <= a - 1; -- decrement when others => f <= (others => '0'); end case; end process; end behavior; -- shifter .vhd library ieee ; use ieee.std_logic_1164.all ; entity

FPGA, VHDL & Verilog ·KleinBagel ·2018-10-25 21:29 ·6 Replies

PDF

2018_NCAA_Mittal_FPGA_Accelerator_CNN.pdf

1.+1) +(+1.-1+(+1.+1) 3 -1 +1 +1 -1 +1 +(+1.+1) +(+1.-1+(+1.+1) 000 -1-1-1= -3 101 001 -1-1+1 = -1 111 (a) An example of binarized MM 010 -1+1-1= -1 111 011 -1+1+1= +1 001 T 0 0 1 BCNT(XNOR(011,011)) 100 +1-1-1= -1 111 0 1 1 1 0 1 BCNT(XNOR(011,000)) 3 -1 +1 101 +1-1+1= +1 001 BCNT(XNOR(011,111)) 1 0 1 110 +1+1-1= +1 001 (b) Binarized MM using XNOR and BCNT. -1 is represented using 0. 111 +1+1+1= +3 011 (c) BCNT using a lookup table (OUT is in 2’s complement form) Fig. 8. (a) An example of binarized MM (b) Implementing binarized MM using XNOR and BCNT (bit-count) functions (c) Implementing

in „Survey on FPGA-based Accelerators for CNNs“ · FPGA, VHDL & Verilog · 2018-10-07 05:00

Article

LPC-Mikrocontroller

Source Lock. User Manual der LPC11-Familie (PDF) Besonderes Augenmerk möchte ich auf die neue Serie LPC111xFD legen, denn in jetzt gibt es den Cortex-M0 auch im DIL 28 den LPC1114FN28 Des Weiteren sind damit SO20, sowie TSSOP20 und TSSOP28 Bauformen verfügbar Eckdaten LPC12xx (Cortex-M0). Die Low Power LPC12xx-Serie

Article ·2018-09-30 05:55

Thread

Weird warning for my design

SCORE_Inter <= DelIy_i_j_1; //C 3'b110: SCORE_Inter <= LUT; //A 3'b111: SCORE_Inter <= 0; //- (output 0) default: SCORE_Inter <= 0; //- (output 0) endcase end endmodule [/code] Based on the attached waveform,the 1st

FPGA, VHDL & Verilog ·dayana42200 ·2018-09-19 02:34 ·17 Replies

PDF

Modeling_and_Implementation_of_FPGA___Based_Flexible_Voltage-to-Frequency_Converter.pdf

in,max=1,5V corresponds to Sofia, 2010 (in Bulgarian). fout=90kHz and V in,min 900mV corresponds to 111

in „Simulink Voltage-to-Frequency Converter on matlab.“ · FPGA, VHDL & Verilog · 2018-05-22 18:01

Thread

ADC on DEO NANO not working

rising_edge(CLK_50); rst_btn_sr <= rst_btn_sr(1 downto 0) & (NOT BTN_RST); if (rst_btn_sr = "111") then reset_me <= '1'; else reset_me <= '0'; end if; end process reset_btn_proc; --RESET process reset_proc :process begin wait until rising_edge(CLK

FPGA, VHDL & Verilog ·chinmaye ·2018-04-25 01:22 ·3 Replies

File

avrdude_out.txt

data avrdude: avr_read(): skipping page 110: no interesting data avrdude: avr_read(): skipping page 111: no interesting data avrdude: avr_read(): skipping page 112: no interesting data avrdude: avr_read(): skipping page 113: no interesting data avrdude: avr_read(): skipping page 114: no interesting data

in „avrdude braucht lange zum Beenden (Linux)“ · Mikrocontroller und Digitale Elektronik · 2018-03-05 12:11

File

filter_tb.v

filter_in_data_log_force[ 109] <= 10'h000; filter_in_data_log_force[ 110] <= 10'h000; filter_in_data_log_force[ 111] <= 10'h000; filter_in_data_log_force[ 112] <= 10'h000; filter_in_data_log_force[ 113] <= 10'h000; filter_in_data_log_force[ 114] <= 10'h000; filter_in_data_log_force[ 115] <= 10'h000; filter_in_data_log_force

in „Implement FIR filter in verilog using FDA tool“ · FPGA, VHDL & Verilog · 2018-01-30 08:22

File

control_pomme.vhd

(shift_reg(137) xor shift_reg(116)); when 140 => shift_reg(1) <= not (shift_reg(140) xor shift_reg(111)); when 142 => shift_reg(1) <= not (shift_reg(142) xor shift_reg(121)); when 145 => shift_reg(1) <= not (shift_reg(145) xor shift_reg( 93)); when 148 => shift_reg(1) <= not (shift_reg(148) xor shift_reg

in „SNAKE GAME VHDL“ · FPGA, VHDL & Verilog · 2018-01-03 11:52

Thread

Integer Assignment to STD_LOGIC_VECTOR

: o=8’d1; In my VHDL case statement I could come up with the below assignment case d is when "111" => o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8)); Is there an easier way of doing the same without using Type conversions in VHDL. Something like the code below (Although this will return a compile error

#5221815: > In my VHDL case statement I could come up with the below assignment > case d is > when "111" => o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8)); > > Is there an easier way of doing the same without using Type conversions > in VHDL. There are literals in VHDL. It's either like x"1" or 16#1#. You

FPGA, VHDL & Verilog ·Rejoy Mathews ·2017-11-26 22:18 ·3 Replies

PDF

ST6285.pdf

Reset 000 001 Input state) Output Output Open Drain 100 101 Open Drain Output Output Push-pull 110 111 Push-pull Note *. xxx = DDR, OR, DR Bits respectively 35/76 35 ST62T85B/E85B I/O PORTS (Cont’d) Table 13. I/O Port configuration for the ST62T85B/E85B MODE AVAILABLE ON (1) SCHEMATIC PA4-PA7 Input PB0

in „Blaupunkt/Audi(??) delta CC Radio remote control protocol“ · µC & Digital Electronics · 2017-11-18 16:05

File

spim.v

reg [2:0]curr; reg shifting; reg loading; reg done; reg w1,w2; reg [7:0]sreg; wire s8b=(bin2gray(3'b111)==bitctr); wire firstbit=(bin2gray(3'b000)==bitctr); wire [2:0]bitctr; always @(posedge clk or posedge rst) if(rst) begin s1<=`S_IDLE; curr<=`CMD_NONE; end else case(s1) `S_IDLE: if(done && req) begin

in „Verilog Simple SPI Code?“ · FPGA, VHDL & Verilog · 2017-09-23 23:33

PDF

de1_v11a.pdf

LVDS93p LVDS108p AB12 FLASH_A16 SRAM_A5 AB10 LVDS110p LVDS125p Y5 SRAM_A17 W16 LVDS94n SRAM_A8 V11 LVDS111n LVDS126n AA4 SRAM_A2 Y17 LVDS94p SRAM_A9 W11 LVDS111p LVDS126p AB4 SRAM_A3 FLASH_A6 V15 AA3 SRAM_A0 FLASH_A5 U15 LVDS95n SRAM_A10 R11 LVDS127n AB3 SRAM_A1 LVDS95p SRAM_A11 T11 LVDS112n LVDS127p T16

in „FPGA active serial programming“ · FPGA, VHDL & Verilog · 2017-09-01 10:36

Thread

Internal signals in vhdl

ms; pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; wait; end process; end; [/vhdl]

pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; ifc_ad0_7 <= "ZZZ"; BD_SEL_PLD <= '1'; HS_PG00D_PLD <= '0'; HS_FLT_PLD <= '0'; ifc_cs3_n <= '0'; -- low active ifc_oe_n <= '0'; -- low active ifc_we_n <

FPGA, VHDL & Verilog ·Hareesh Mohanan ·2017-08-25 18:42 ·7 Replies

Article

RFM12

(:8) 010 = 1, 6 MHz (:6) 011 = 2 MHz (:5) 100 = 2,5 MHz (:4) 101 = 3, 3 MHz (:3) 110 = 5 MHz (:2) 111 = 10 MHz rowspan=3|v rowspan=3|voltage rowspan=3|Bestimmt die Betriebsspannung, bei der der RFM12 einen Unterspannungs-Interrupt auslöst. Im Power-Managment muss das eb-Bit aktiv sein, damit dies funktioniert

000 = reserviert 001 = 400 kHz 010 = 340 kHz 011 = 270 kHz 100 = 200 kHz 101 =134 kHz 110 = 67 kHz 111 = reserviert rowspan=4|g rowspan=4|lna gain select rowspan=4|Verstärkungsfaktor des UHF-Verstärkers am Eingang (LNA = Low Noise Amplifier, als ob das nicht selbstverständlich ist). Werte in dBm (Dezibel

Article ·2017-07-10 06:54

Thread

ERSA 111 ms60

for you! You can find (German language) an interesting article regarding the substitution of ERSA111 IC, and the solution seems very simple ERSA111==LM324! The link is: https://www.fingers-welt.de/phpBB/viewtopic.php?t=7438 I hope this may be helpful for you best pienne

> ... the solution seems very simple ERSA111==LM324 Ouch. After five years, just for the records: https://www.mikrocontroller.net/topic/544326#new

Analog Circuits ·Guilherme Lopes ·2022-10-19 16:46 ·7 Replies

File

i2c_master_top.txt

could change in future releases -- when "101" => wb_dat_o <= txr; when "110" => wb_dat_o <= cr; when "111" => wb_dat_o <= (others => '0'); when others => wb_dat_o <= (others => 'X'); -- for simulation only end case; end if; end process assign_dato; -- generate registers (CR, SR see below) gen_regs: process

in „Connect FPGA with i2c to a mikrocontroller“ · FPGA, VHDL & Verilog · 2017-05-29 14:26

Article

Sinusgenerator mit IIR-Filter

. als PDF auf der Webseite des Autors Clay Turner (IEEE Signal Processing Magazine, Mai 2003 S.103-111)

Article ·2017-05-29 05:02

File

fivebit.vhd

<= data; --Circular left shift elsif SEL = "110" then data <= data; --1s' complement elsif SEL = "111" then data <= data; --2s' complement (SEL = "111") end if; end if; end process; end Behavioral;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-23 16:09

File

five_bit_tb.vhd

101"; wait for 60 ns; --Circular left shift SEL <= "110"; wait for 60 ns; --1s' complement SEL <= "111"; wait for 60 ns; --2s' complement SEL <= "000"; wait for 10 ns; --Reset SEL <= "001"; wait; --Parallel loading end process; END;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-23 16:09

File

five_bit_tb.vhd

clockk_period*8; SEL <= "101"; wait for clockk_period*8; SEL <= "110"; wait for clockk_period*8; SEL <= "111"; wait for clockk_period*8; SEL <= "000"; wait for clockk_period; SEL <= "001"; wait; end process; END;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-22 23:32

File

mux_8x1.vhd

011" => Y <= I(3); when "100" => Y <= I(4); when "101" => Y <= I(5); when "110" => Y <= I(6); when "111" => Y <= I(7); when others => Y <= '0'; end case; end process; end Behavioral;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-21 11:49

Thread

VHDL project : 5 bit shift reg

110" (6). what should happen with every rising clock? data <= ? And what should happen if SEL = "111" (7)?

complement when others => data <= std_logic_vector(unsigned(not data) +1); --2s' complement (SEL = "111")[/vhdl]

FPGA, VHDL & Verilog ·Michael ·2017-04-24 13:54 ·42 Replies

File

spi_master.v

else if (sck_q == spi_control[3:0]) begin ctr_d = ctr_q + 1'b1; // count the shifted bit if(ctr_q==3'b111) begin // 1 byte already shifted out state_d=IDLE; data_out_d = data_q; // Received a full byte, so set notification bit spi_status_d[0] <= 1'b1; // Reset start bit, so user can start next transfer

in „Verilog Simple SPI Code?“ · FPGA, VHDL & Verilog · 2017-04-05 22:29

File

gdb_log.txt

JLINK_IsHalted() returns FALSE (0002ms, 1872ms total) 02-00000000-00-00020112-0048: TBA7FC700 020:111 JLINK_IsHalted() returns FALSE (0002ms, 1872ms total) 02-00000000-00-00020134-0048: TBA7FC700 020:134 JLINK_IsHalted() returns FALSE (0001ms, 1871ms total) 02-00000000-00-00020157-0048: TBA7FC700 020

in „Problem mit Breakpoints (Eclipse + JLink)“ · Mikrocontroller und Digitale Elektronik · 2017-01-18 13:56

Thread

Resetting Registers on Digital Clock Manager Output

reg [3 : 0] SR; always @ (posedge CLKIN) begin if(RESET) begin SR [3 : 0] <= 4'b111; LOCKED_R <=0; end else begin LOCKED_R <= LOCKED; if(LOCKED < LOCKED_R | STATUS [1] )// H to L LOCKED | CLKIN UNSTABLE SR <= {1'b1 , SR[3 : 1]}; else SR <= {1'b0 , SR[

FPGA, VHDL & Verilog ·Ahmed Abbasi ·2016-11-21 18:00 ·3 Replies

Thread

PS2 Keyboard and RAM block interaction Verilog

case (hex_digit) 4'h0: segments = 7'b100_0000; 4'h1: segments = 7'b111_1001; 4'h2: segments = 7'b010_0100; 4'h3: segments = 7'b011_0000; 4'h4: segments = 7'b001_1001; 4'h5: segments = 7'b001_0010; 4'h6: segments = 7'b000_0010; 4'h7: segments = 7'b111_1000; 4'h8: segments = 7'b000_0000; 4'h9: segments = 7'b001_1000; 4'hA: segments = 7'b000_1000; 4'hB: segments = 7'b000_0011; 4'hC: segments

FPGA, VHDL & Verilog ·Sarah ·2016-11-20 23:17 ·1 Replies

PDF

spansion_S34ML01G2_04G2__1_-467068_flash.pdf

blocks 01h, 03h 110 M Number of programs per page 04h Partial programming attributes 5-7 Reserved 111 M 4 1 = partial page layout is partial page data followed by 00h partial page spare 1-3 Reserved 0 1 = partial page programming has constraints 112 M Number of bits ECC correctability 04h Number of

in „VHDL CODE FOR READ AND WRITE PAGE TO NAND FLASH MEMORY“ · FPGA, VHDL & Verilog · 2016-10-05 22:22

Thread

vhdl code simulation

"101", not alu_arm1 when "110", not alu_arm2 when "111", "--------" when others; end behavioral; ----------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all

FPGA, VHDL & Verilog ·Ali abbass Zoraghchian ·2016-08-13 17:35 ·1 Replies

Thread

3 bit output

already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you.

FPGA, VHDL & Verilog ·Ashuuu ·2016-05-03 22:24 ·3 Replies

Thread

Verilog buffer implementation problem

<= 4'b0; FSM_read_state <= ADC_Channel; ADC_CH <= 3'b111; // invalid channel channel_changed <= 1'b0; ch_cng_cnt <= 0; end else begin case(FSM_read_state) ADC_Channel: begin

FPGA, VHDL & Verilog ·H Karim ·2016-03-09 06:36 ·1 Replies

File

main_medium.lst

= 2; \ 000020 A881 MOV R0,SP \ 000022 7602 MOV @R0,#0x2 109 uint8 len = 1; 110 uint16 offset = 0; 111 uint8 method = 0; 112 113 114 value ++; \ 000024 06 INC @R0 115 116 while(1) { 117 WriteAttrCB( 0, (gattAttribute_t*)&att, (uint8*)&value, len, offset, method ); \ ??main_0: \ 000025 ; Setup parameters

in „IAR (8051) immer noch mit Bug“ · Mikrocontroller und Digitale Elektronik · 2016-02-28 00:48

Thread

control logic for memory selection

eg:if control signal is 00 memory1 is selected and my address counter starts counting from 000 to 111 (data also sent in parellel)...once complete....then sample next control signal for writing memory2...

previous control signal is generated....ie if i select ctrl to be 00 then addr counts from 000 to 111 even if ctrl changes in between it does not matter..

FPGA, VHDL & Verilog ·felix89 ·2016-02-24 16:32 ·2 Replies

Thread

I don't really understand how VGA controlling works

from submodules that decides the "shapes" of objects on screen 3'b ??1: VGA_RGB <= 3'b 111; //white snow 3'b ?10: VGA_RGB <= (color_flag) ? (3'b 110) : (3'b 111); //switching between yellow and white 3'b 100: VGA_RGB <= 3'b 010; //green tree

FPGA, VHDL & Verilog ·Naketo Ito ·2015-12-29 18:54 ·0 Replies

PDF

datashit_spartan_6.pdf

110 ps FG(G)676 134 ps CS(G)484 95 ps LX100 FG(G)484 155 ps FG(G)676 144 ps CS(G)484 88 ps FG(G)484 111 ps LX100T FG(G)676 147 ps FG(G)900 134 ps CS(G)484 84 ps FG(G)484 103 ps LX150 FG(G)676 115 ps FG(G)900 121 ps CS(G)484 83 ps FG(G)484 88 ps LX150T FG(G)676 141 ps FG(G)900 120 ps Notes: 1. These values

in „Spartan 6, PCS/PMA Ethernet 1000BASE-X“ · FPGA, VHDL & Verilog · 2015-12-23 00:10

File

tb_real_test.vhd

architecture Behave of tb_real_test is signal a : real := 23456789.0; begin process (a) variable j : real := 111.1; begin if a=a*j/111.1 then report("equal"); else report("different!"); end process; end;

in „Active-HDL design“ · FPGA, VHDL & Verilog · 2015-12-16 14:37

Thread

Active-HDL design

0.0 then report "2. remainder is zero!"; end if; j := 111.1; if a=a*j/111.1 then report "b) equal!"; else report "b) different!"; end if; if a*j/111.1 mod 1.0 = 0.0 then report "3. remainder is zero!"; end if; j:=a*j/111.1 mod 1.0; report "Should be .0 --> " & real'image(j); end process; end; [/vhdl] Think about the results...

FPGA, VHDL & Verilog ·Nazar Rendzenyak ·2015-12-17 08:12 ·34 Replies

Thread

Instruction set implementation in VHDL

constant BEQ : std_logic_vector(2 downto 0) := "110"; constant JALR : std_logic_vector(2 downto 0) := "111"; -- SIGNALS DECLARATION signal opcode : std_logic_vector(MAXWIDTH-1 downto MAXWIDTH-3); signal regA : std_logic_vector(MAXWIDTH-4 downto MAXWIDTH-6); signal regB : std_logic_vector(MAXWIDTH

FPGA, VHDL & Verilog ·Maxim Moor ·2015-11-30 19:01 ·8 Replies

Article

Entwicklungsboard mit PIC

, die allerdings mit dem gemeinsamen Chip Select Signal und unterschiedlichen HW-Adressen (000 und 111) als I/ O Serial – zu –Parallel Treiber funktionieren. IC2 ist mit 4 Binär zu Dezimal Wandler ausgestattet und wird zur Ausgabe der 16 Bit Daten benutzt. Die ersten 8 Bit vom IC3 können über JP15 mit

Article ·2015-09-20 13:25

File

stm32f10x_rcc.lst

uint32_t)0xFFFFF8FF) 110:lib/stm32f10x_rcc.c **** #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) 111:lib/stm32f10x_rcc.c **** #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) 112:lib/stm32f10x_rcc.c **** #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) 113:lib/stm32f10x_rcc.c **** #define CFGR_ADCPRE_Reset_Mask

in „Seltsame Initialisierungen und Abstürze.“ · Mikrocontroller und Digitale Elektronik · 2015-08-17 15:34

Article

Datei:Ttester ger111k.pdf

Article ·2015-05-01 15:49

Search results for "111"

216 results for 111 Search results for "111"

216 results for 111