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  • Thread

    ERSA 111 ms60

    for you! You can find (German language) an interesting article regarding the substitution of ERSA111 IC, and the solution seems very simple ERSA111==LM324! The link is: https://www.fingers-welt.de/phpBB/viewtopic.php?t=7438 I hope this may be helpful for you best pienne

    > ... the solution seems very simple ERSA111==LM324 Ouch. After five years, just for the records: https://www.mikrocontroller.net/topic/544326#new

    Analog Circuits ·Guilherme Lopes · ·7 Replies

  • Thread

    VHDL project : 5 bit shift reg

    110" (6). what should happen with every rising clock? data <= ? And what should happen if SEL = "111" (7)?

    complement when others => data <= std_logic_vector(unsigned(not data) +1); --2s' complement (SEL = "111")[/vhdl]

    FPGA, VHDL & Verilog ·Michael · ·42 Replies

  • Thread

    Active-HDL design

    0.0 then report "2. remainder is zero!"; end if; j := 111.1; if a=a*j/111.1 then report "b) equal!"; else report "b) different!"; end if; if a*j/111.1 mod 1.0 = 0.0 then report "3. remainder is zero!"; end if; j:=a*j/111.1 mod 1.0; report "Should be .0 --> " & real'image(j); end process; end; [/vhdl] Think about the results...

    FPGA, VHDL & Verilog ·Nazar Rendzenyak · ·34 Replies

  • Thread

    Implementation of MASH 111 in verilog

    I am trying to design MASH 111 DDSM using verilog. I have attatched the code. But output is "xxx" always. Can someone help?

    FPGA, VHDL & Verilog ·GAURAV G. · ·1 Replies

  • Thread

    Verilog circuit

    b and c connected at the bottom of the MUX? The left input is b, then a and right is c. So 000 ... 111 is a combination of b, a, c. In VHDL it would be: signal sel := std_logic_vector(2 downto 0); begin sel <= b & a & c; with sel select y <= a and b when "000", c when "001

    3'b111: y = a ^ b; endcase end assign sel = b & a & c;

    FPGA, VHDL & Verilog ·Mattia · ·4 Replies

  • Thread

    decoder in vhdl dont work in simulation.

    then f<="00000100" after 1 ps; elsif a="110" then f<="00000010" after 1 ps; elsif a="111" then f<="00000001" after 1 ps; else null; end if; end if; end process; end bhv; [/vhdl]

    010" after 20ns, "011" after 30ns, "100" after 40ns, "101" after 50ns, "110" after 60ns, "111" after 70ns, "000" after 80ns, "001" after 90ns, "010" after 100ns, "011" after 110ns, "100" after 120ns, "101" after 130ns, "110" after 140ns, "111" after 150ns; END; [/vhdl]

    FPGA, VHDL & Verilog ·ee_vhdl · ·5 Replies

  • Thread

    Display 640x480 Nexys 3 board

    --------------------------------------- if hcounter < 640 and vcounter < 480 then red<= "111"; green<="111"; blue<="11"; hsync<='1'; vsync<='0'; else red<= "111"; green<="111"; blue<="11"; hsync<='1'; vsync<='0'; end if; ----------

    FPGA, VHDL & Verilog ·sketchy · ·8 Replies

  • Thread

    Internal signals in vhdl

    ms; pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; wait; end process; end; [/vhdl]

    pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; ifc_ad0_7 <= "ZZZ"; BD_SEL_PLD <= '1'; HS_PG00D_PLD <= '0'; HS_FLT_PLD <= '0'; ifc_cs3_n <= '0'; -- low active ifc_oe_n <= '0'; -- low active ifc_we_n <

    FPGA, VHDL & Verilog ·Hareesh Mohanan · ·7 Replies

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