1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | entity LB_src is
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6 | -- generic (NUM_LB : integer := 4 );
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7 | Port ( clk, i_lVal, i_fVal, n_rst : in std_logic;
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8 | i_data : in std_logic_vector(7 downto 0);
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9 |
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10 | o_lVal, o_fVal : out std_logic;
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11 | -- o_data : out std_logic_vector(8*(NUM_LB+1)-1 downto 0) );
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12 | o_data : out std_logic_vector(39 downto 0) );
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13 | end LB_src;
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14 |
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15 | architecture Behavioral of LB_src is
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16 |
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17 | ---- Konstanten
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18 | constant NUM_LB : integer := 4;
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19 | constant ONES_VEC : std_logic_vector(NUM_LB-1 downto 0) := (others => '1');
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20 |
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21 | ---- Komponenten
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22 | component LB_Fifo
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23 | PORT (
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24 | clk : IN STD_LOGIC;
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25 | srst : IN STD_LOGIC;
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26 | din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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27 | wr_en : IN STD_LOGIC;
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28 | rd_en : IN STD_LOGIC;
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29 | dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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30 | full : OUT STD_LOGIC;
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31 | empty : OUT STD_LOGIC
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32 | );
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33 | end component;
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34 |
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35 | ---- Signale
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36 | signal LB_data, LB_data_del, LB_data_del_del : std_logic_vector(i_data'length*(NUM_LB+1) -1 downto 0) := (others => '0');
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37 | signal dout_f1, dout_f2, dout_f3, dout_f4 : std_logic_vector(i_data'range) := (others => '0');
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38 | signal i_data_sig, i_data_sig_del : std_logic_vector(i_data'range) := (others => '0');
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39 |
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40 | signal f_full_REG, f_empty_REG, f_empty_REG_del, f_wr_REG, f_rd_REG, mask_wr, mask_rd : std_logic_vector(NUM_LB-1 downto 0) := (others => '0');
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41 | signal lVal_REG, fVal_REG : std_logic_vector(NUM_LB downto 0) := (others => '0');
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42 | signal last_line_cnt : unsigned(NUM_LB downto 0) := (others => '0');
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43 |
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44 | signal lVal_sig, fVal_sig, r_edge_lVal, f_edge_lVal, r_edge_fVal, f_edge_fVal : std_logic := '0';
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45 |
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46 | signal ONES_WITH_ZERO_VEC : std_logic_vector(NUM_LB-1 downto 0) := (others => '1');
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47 |
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48 | begin
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49 |
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50 | -- Fifo Instanziierung
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51 | Fifo0 : LB_Fifo
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52 | port map(clk => clk, srst => (not n_rst), din => i_data_sig, wr_en => f_wr_REG(0),
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53 | rd_en => f_rd_REG(0), dout => dout_f1, full => f_full_REG(0), empty => f_empty_REG(0));
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54 |
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55 | Fifo1 : LB_Fifo
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56 | port map(clk => clk, srst => (not n_rst), din => dout_f1, wr_en => f_wr_REG(1),
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57 | rd_en => f_rd_REG(1), dout => dout_f2, full => f_full_REG(1), empty => f_empty_REG(1));
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58 |
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59 | Fifo2 : LB_Fifo
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60 | port map(clk => clk, srst => (not n_rst), din => dout_f2, wr_en => f_wr_REG(2),
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61 | rd_en => f_rd_REG(2), dout => dout_f3, full => f_full_REG(2), empty => f_empty_REG(2));
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62 |
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63 | Fifo3 : LB_Fifo
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64 | port map(clk => clk, srst => (not n_rst), din => dout_f3, wr_en => f_wr_REG(3),
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65 | rd_en => f_rd_REG(3), dout => dout_f4, full => f_full_REG(3), empty => f_empty_REG(3));
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66 |
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67 | ONES_WITH_ZERO_VEC(0) <= '0';
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68 |
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69 | o_data <= LB_data;
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70 | LB_data <= dout_f4 & dout_f3 & dout_f2 & dout_f1 & i_data_sig_del;
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71 |
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72 | r_edge_lVal <= i_lVal AND (NOT lVal_sig);
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73 | f_edge_lVal <= (NOT i_lVal) AND lVal_sig;
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74 |
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75 | f_edge_fVal <= (NOT i_fVal) AND fVal_sig;
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76 |
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77 | CONTROLL_FIFOS: process(clk) begin
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78 | if rising_edge(clk) then
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79 | if n_rst = '0' then
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80 | lVal_REG <= (others => '0');
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81 | fVal_REG <= (others => '0');
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82 |
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83 | o_lVal <= '0';
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84 | o_fVal <= '0';
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85 |
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86 | mask_wr(mask_wr'left downto 1) <= (others => '0');
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87 | mask_rd(mask_rd'left downto 1) <= (others => '0');
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88 | mask_wr(0) <= '1';
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89 |
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90 | last_line_cnt <= (others => '0');
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91 |
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92 | else
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93 | i_data_sig <= i_data;
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94 | i_data_sig_del <= i_data_sig;
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95 |
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96 | f_empty_REG_del <= f_empty_REG;
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97 | lVal_sig <= i_lVal;
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98 | fVal_sig <= i_fVal;
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99 |
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100 |
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101 | if r_edge_lVal = '1' and i_fVal = '1' then
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102 | f_wr_REG(0) <= '1';
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103 | f_rd_REG <= mask_rd(mask_rd'left downto 0);
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104 |
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105 | fVal_REG <= fVal_REG(fVal_REG'left-1 downto 0) & '1';
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106 | lVal_REG <= lVal_REG(lVal_REG'left-1 downto 0) & '1';
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107 |
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108 | -- i_lVal ist mindestens für einen Takt auf '1'-Pegel
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109 | elsif i_lVal = '1' and i_fVal = '1' then
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110 | o_lVal <= lVal_REG(lVal_REG'left);
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111 | o_fVal <= fVal_REG(fVal_REG'left);
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112 | f_wr_REG <= mask_wr;
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113 | end if;
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114 |
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115 | -- fallende Flanke i_lVal
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116 | if f_edge_lVal = '1' and i_fVal = '1' then
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117 | f_rd_REG <= (others => '0');
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118 | f_wr_REG(0) <= '0';
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119 |
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120 | mask_wr <= mask_wr(mask_wr'left-1 downto 0) & '1' ;
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121 | mask_rd <= mask_rd(mask_rd'left-1 downto 0) & '1' ;
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122 |
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123 | -- i_lVal ist mindestens einen Takt auf '0'-Pegel
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124 | elsif i_lVal = '0' and i_fVal = '1' then
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125 | o_lVal <= '0';
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126 |
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127 | f_rd_REG <= (others => '0');
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128 | f_wr_REG <= (others => '0');
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129 | end if;
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130 |
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131 | -- fallende Flanke i_fVal -> Frame ist vorbei
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132 | if f_edge_fVal = '1' then
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133 | last_line_cnt <= last_line_cnt + 1;
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134 | f_rd_REG <= (others => '0');
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135 | f_wr_REG(0) <= '0';
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136 | mask_wr <= mask_wr(mask_wr'left-1 downto 0) & '0';
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137 |
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138 | -- Letzte Zeilen -> d.H. Fifos nacheinander leer lesen
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139 | elsif f_edge_fVal = '0' and i_fVal = '0' and unsigned(f_empty_REG) = 0 then
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140 | f_rd_REG <= mask_rd(mask_rd'left downto 0);
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141 | f_wr_REG <= (others => '0');
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142 | o_lVal <= '0';
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143 | end if;
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144 |
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145 | -- last_line_cnt = 1 -> Aufhören in Fifo zu schreiben, o_lVal ein Takt ausschalten und last_line_cnt hochzählen
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146 | if last_line_cnt = 1 then
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147 | f_wr_REG <= (others => '0');
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148 |
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149 | o_lVal <= '0';
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150 | last_line_cnt <= last_line_cnt + 1;
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151 |
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152 | -- last_line_cnt = 2 -> o_lVal wieder einschalten, Letzte Zeilen aus Fifos raus-lesen bzw. rein-schreiben
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153 | elsif last_line_cnt = 2 then
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154 | o_lVal <= lVal_REG(lVal_REG'left);
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155 | f_wr_REG <= mask_wr;
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156 | f_rd_REG <= mask_rd(mask_rd'left downto 0);
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157 | end if;
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158 |
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159 | -- Das Erste / Ein weiteres Fifo ist leer.
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160 | if f_empty_REG /= f_empty_REG_del and last_line_cnt = 2 then
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161 |
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162 | mask_rd <= mask_rd(mask_rd'left-1 downto 0) & '0';
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163 | mask_wr <= mask_wr(mask_wr'left-1 downto 0) & '0';
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164 |
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165 | f_rd_REG <= (others => '0');
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166 | f_wr_REG <= (others => '0');
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167 |
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168 | o_lVal <= '0';
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169 |
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170 | -- Alles Fifos sind leer
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171 | if f_empty_REG = ONES_VEC then
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172 | o_fVal <= '0';
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173 |
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174 | mask_wr(0) <= '1';
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175 | mask_rd <= (others => '0');
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176 |
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177 | lVal_REG <= (others => '0');
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178 | fVal_REG <= (others => '0');
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179 | last_line_cnt <= (others => '0');
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180 | end if;
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181 | end if;
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182 | end if;
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183 | end if;
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184 | end process CONTROLL_FIFOS;
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185 |
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186 | end Behavioral;
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