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Forum: FPGA, VHDL & Verilog How to generate Trigger for 500ns in Verilog ?


How to generate Trigger for 500ns in Verilog ?
von Saraswathy S. (saras015)

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I am working with FPGA board. For my test, i am going to add the trigger 
logic in one side [One PC], and in other side the counter design will be 
added in XILIXN VIVADO and should start to give its counter after 
receiving the trigger signal.

For every trigger [500ns], the counter should start. To execute this 
task, i need the verilog code for Creating the Trigger Signal.
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module counter(

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    input clk,

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    input reset,

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    output [127:0] counter_out,

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    output trig

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    );

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    reg trig=0;

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    reg [127:0] counter_out=0;

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    reg [7:0] temp=0;

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    always@(posedge clk)

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    begin

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    if(~reset)

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        begin

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        trig<=0;

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        counter_out<=0;

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        end

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    else

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        begin

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        counter_out<=counter_out+1;

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        temp<=temp+1;

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        if(temp==25)

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            begin

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            temp<=0;

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            trig<=~trig;

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            end

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        end

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    end

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endmodule

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