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Forum: FPGA, VHDL & Verilog Checking the validity of std_logic_vector value @testbench


Author: VHDL learner (Guest)
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Hi Experts,

what is the easiest way to check whether a std_logic_vector value has 
invalid/uninitialized bit(s) in it (such as 'X', 'U', 'Z'). VHDL-2008 
would be okay.

Regards...

Author: Duke Scarring (Guest)
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I would write a function:
    function has_X( value : std_logic_vector) return boolean is
    begin
        for index in value'range loop
            if value( index) = 'X' then
                return true;
            end if;
        end loop;
        return false;
    end function has_X;

Duke

Author: Ottmar (Guest)
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This function is already defined in std_logic_1164.

Excerpt:
    FUNCTION Is_X ( s : std_logic_vector  ) RETURN  BOOLEAN IS
    BEGIN
        FOR i IN s'RANGE LOOP
            CASE s(i) IS
                WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
                WHEN OTHERS => NULL;
            END CASE;
        END LOOP;
        RETURN FALSE;
    END;

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