Forum: FPGA, VHDL & Verilog arbiter using verilog

Author: ANURAG SHANKHDHAR (Company: student) (anurag3939)
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hello everyone,
             i have given an assignment in which i want to design an 
arbiter who takes input from a fifo. FIFO has width of 32 bit and we 
need to divide these bits into sub packets of where first two bits 
contains the head or tail or normal or no flit of fifo and next three 
bits contains the addres of grant of arbiter.... if anyone have any idea 
plzzz reply :)


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