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Forum: FPGA, VHDL & Verilog problem in 2d- dct computation


Author: Ajay Mittal (Guest)
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new.vhd is vhdl code another is testbench code.
It is program for 2-d DCT(Discrete cosine transform).
Assumed to take eight 16 bit inputs in first 8 clock cycles. This will 
compute the rowwise dct first then in next eight clock cycles column 
wise dct will be calculated.
but at present no output is coming.

Please neglect logical mistakes. Only help me with syntax or other
mistakes.
Its urgent so please help me out guys.

Author: Ajay Mittal (Guest)
Posted on:
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sorry this is the correct .vhd file....

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