Forum: FPGA, VHDL & Verilog How data is distributed among memory from external source to FPGA.

Author: Junior Hpc (Company: University) (junior_hpc)
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Hello. I have a theoretical question.

I have a Xilinx Artix 7 ac701 with the following features:
-Distributed RAM: 2888 Kbyte
-Shift register: 1444 Kbyte
-Block RAM: 13140 Kbyte

My first application is based on Xillybus, in which my Java application 
copy some data from a text file to write_device_file. As soon as data is 
ready on write_device_file, the VHDL application running on FPGA 
processes those data and as soon as data has been processed the VHDL 
application copies those processed data from FPGA to read_device_file.

Now, I have some doubts.

-1: in which memory (Distributed RAM, Shift register or B RAM) is copied 
the data from write_device_file to FPGA? This is not clear to me. I 
guess the data is copied on all these memory but I am not sure.

-2: Are there any other memory in which data can be copied from 
write_device_file to FPGA? Well, the reason why I am asking is that I 
can set the buffer size in my Java app. The more buffer size is bigger, 
the better perfomance I get from my Java app. E.g., if I set the buffer 
size 1MB, the data is copied is less time than setting the buffer size 
to 512KB. What I don't understand is what happened if I set a buffer 
size bigger than available memory on FPGA.

-3: I have attached the design of my application. As you can see, only 
few components have been configured during the bitfile generation. Are 
there also memories in those components not configured?



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