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Forum: FPGA, VHDL & Verilog wire connection help


Author: wire (Guest)
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Hi
Could you please explain How I can connect my B,C,D to my displays with 
command "wire" instead of calling modules?
had tried to read FAQ about that, but still don't get it...


module divide(A,B,C,D);

input [9:0] A;
output [3:0] B,C,D;
reg [6:0] B,C,D;

always @ (A)

begin

B=A/100;
C=A%100/10;
D=A%100%10;

end

display  HUN (B,a);
display  TEN (C,a);
display  ONE (D,a);
endmodule



module display (a,Led);

input [3:0] a;
output [6:0] Led;
reg [6:0] Led;
always @ (a)
//and just code for my led

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