I want to test my CRC encoder/decoder by sending packet based data by hdl test bench, i have sent byte by byte data on each clock cycle and store it on ram memory locations,and test it successfully.Now next step to test my design is to take packet based data how can i handle it with ease and generate from test bench i tried it as follow for data generation? //32-byte packet. reg [255:0] data; data=256'hABCD......01(a total length of 32 byte) kindly guide me as i am new-by to hdl.
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