Forum: FPGA, VHDL & Verilog Basic memory unit help

Author: Omar Rashad (Guest)
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I get the following error when comiling:

The symbol to_int does not have a visible declaration.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Mem is
generic (N: integer; -- N bits wide (# of columns)
         K: integer); -- K bits long (# of rows)
port (Din: IN std_logic_vector (N-1 downto 0);
      clk,rw_en: IN std_logic;
      add_in: IN std_logic_vector (K-1 downto 0);
      Dout: OUT std_logic_vector (N-1 downto 0));
end Mem;

architecture behavior of Mem is
type mem_array is array (2**K-1 downto 0) of std_logic_vector (N-1 downto 0);
signal our_array: mem_array := (others =>(others => '0'));


process (clk, Din, rw_en, add_in)
--variable address: integer;
  if (clk = '1' and clk'event) then
    if (rw_en = '1') then
      our_array (to_int(unsigned(add_in))) <= Din;
      Dout <= our_array (to_int(unsigned(add_in)));
    end if;
  end if;
end process;
end behavior;

Author: Lothar Miller (lkmiller) (Moderator)
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The function is called "to_integer()"...

Try this with Google translator, its German: 

: Edited by Moderator
Author: Omar Rashad (Guest)
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Thank you. My bad....


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