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Forum: FPGA, VHDL & Verilog Unit testing- too much maintenance overhead?


Author: R L (Guest)
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Hi, all,
I will be happy to hear your thoughts on this.

I'm working on some complex designs, with ten or more subunits. I know 
its often recommended, in the software world, to do unit level testing, 
as well as design-level testing, but i find that later maintaining those 
testbenches is very time consuming.

so, how do you simulate and test your designs? On what level?
Note - im bot talking about verification here, just testing as part of 
the design process itself.

Thx,
RL

Author: P. K. (pek)
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If you can simulate (which you most probably refer to as "testing") your 
sub blocks embedded within the higher entity, no problem.

However, sometimes it's easier to simulate lower level entities 
standalone (doing it the "divide and conquer" way). You may better reach 
special conditions and be sure it works before going to a greater 
context. Depends on how complex your "complex designs" are...

Author: Colibri (Guest)
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As soon as full test coverage is demanded, there is no other way than 
simulating at block level

Author: P. K. (pek)
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And of course it's a big difference whether your design goes into an 
FPGA (simulate, among other reasons, to avoid to many synthesis 
iterations) or into an ASIC (full coverage required, as masks are 
expensive) ...

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