EmbDev.net

Forum: FPGA, VHDL & Verilog Top module problems..


Author: John Mayer (215)
Posted on:

Rate this post
0 useful
not useful
I generated a fifo buffer using IP core, and are now having problem 
using it.

I made This is my top module
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
    Port ( 
        Mclk:  in std_logic;
        LED : out  STD_LOGIC_VECTOR (5 downto 0);
        LEDf: out std_logic;
        LEDE: out std_logic;
           BTN : in  STD_LOGIC_VECTOR (3 downto 0);
           Switch : in  STD_LOGIC_VECTOR (7 downto 0));
end top;
architecture Behavioral of top is

Component FIFO IS
  PORT (
    clk : IN STD_LOGIC;
    rst : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(98 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(98 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC
  );
END component;
begin
process(Mclk)
begin
if rising_edge(mclk) then 
  clk <= mclk;
  LEDf <= full; 
  LEDe <= empty; 
  wr_en<= BTN(0); 
  rd_en<= BTN(1);
  rst <= BTN(2); 
  din <= switch;
  dout <= LED;
end if;
end process;
end Behavioral;

why isn't this working, it isn't recognizing the input ports on my 
fifo.. these are the error messages.
Line 59. Undefined symbol 'clk'.
Line 60. Undefined symbol 'full'.  Should it be: null?
Line 60. full: Undefined symbol (last report in this block)
Line 61. Undefined symbol 'empty'.
Line 61. empty: Undefined symbol (last report in this block)
Line 62. Undefined symbol 'wr_en'.
Line 63. Undefined symbol 'rd_en'.
Line 64. Undefined symbol 'rst'.
Line 65. Undefined symbol 'din'.  Should it be: in or min?
Line 66. Undefined symbol 'dout'.  Should it be: out?

Author: Clem (Guest)
Posted on:

Rate this post
0 useful
not useful
It doesn't know any or your ports (not just your input).
You have to instantiate your FIFO.
Have a look at a easy port map example.
e.g. 
https://www.doulos.com/knowhow/vhdl_designers_guid...

Author: John Mayer (215)
Posted on:

Rate this post
0 useful
not useful
I am not quite sure on how i should instantiate a component?
isn't what iam doing with component in my arcitecture?

-- EDIT--

entity top is
    Port ( 
        Mclk:  in std_logic;
        LED : out  STD_LOGIC_VECTOR (5 downto 0);
        LEDf: out std_logic;
        LEDE: out std_logic;
           BTN : in  STD_LOGIC_VECTOR (3 downto 0);
           Switch : in  STD_LOGIC_VECTOR (7 downto 0));
end top;
architecture Behavioral of top is

Component FIFO IS
  PORT (
    clk : IN STD_LOGIC;
    rst : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(98 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(98 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC
  );
END component;
begin

G1: FIFO Port map (clk <= mclk , LEDf <= full, LEDe <= empty, wr_en<= BTN(0), rd_en<= BTN(1),rst <= BTN(2),din <= switch,dout <= LED); 
end Behavioral;

Errors:
Line 57. Undefined symbol 'clk'.
Line 57. clk: Undefined symbol (last report in this block)
Line 57. Undefined symbol 'full'.  Should it be: null?
Line 57. full: Undefined symbol (last report in this block)
Line 57. Undefined symbol 'empty'.
Line 57. empty: Undefined symbol (last report in this block)
Line 57. Undefined symbol 'wr_en'.
Line 57. wr_en: Undefined symbol (last report in this block)
Line 57. Undefined symbol 'rd_en'.
Line 57. rd_en: Undefined symbol (last report in this block)
Line 57. Undefined symbol 'rst'.
Line 57. rst: Undefined symbol (last report in this block)
Line 57. Undefined symbol 'din'.  Should it be: in or min?
Line 57. din: Undefined symbol (last report in this block)
Line 57. Undefined symbol 'dout'.  Should it be: out?
Line 57. dout: Undefined symbol (last report in this block)
Line 57. IN mode Formal clk of FIFO with no default value must be associated with an actual value.

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
How does this fifo look like? Is there a entity "fifo"?

Author: John Mayer (215)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Not in my Top module, but i have a VHDL module called Fifo, which is 
generated by using the IP core

The FIFO vhd file is attached.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.