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Forum: FPGA, VHDL & Verilog error: * can not have such operands in this context


Author: Mariem Makni (Company: enis) (makni)
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Hi,

I am trying to multipy an std_logic_vector with a negatif number :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mul_main is
    Port ( a :in  STD_LOGIC_VECTOR( 0 to 7);
        clk: in  STD_LOGIC;
           c :out STD_LOGIC_VECTOR(0 to 15)
        );
end mul_main;

architecture Behavioral of mul_main is

begin
p: process(clk)
begin
if (clk' event and clk='1') then
c <= (-2)* a;
end if;
end process;

end Behavioral;

But, I'm getting this error: * can not have such operands in this 
context

In fact, I want to multiply an std_logic_vector with a positif or 
negatif constant , unfortunately, I'm getting the same problem.
Can you help me please.

Thanks in advance

Author: Lothar Miller (lkmiller) (Moderator)
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Mariem Makni wrote in post #355007:
> But, I'm getting this error: * can not have such operands in this
> context
Due to the very strict type checking you cannot multiply an integer and 
a std_logic_vector in VHDL (unless you don't overload the * operator).

> In fact, I want to multiply an std_logic_vector with a positif or
> negatif constant
How can you use the unsigned lib and try to perform a signed 
multiplication?

Use the
> use IEEE.numeric_std.all;
Or the
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
But never ever all of them together!
I advise you to use the signed and unsigned vectors and the conversions 
from the numeric_std.
Try this with Google translator:

http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

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