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Forum: FPGA, VHDL & Verilog testbench in vhdl-ams


Author: sebgimi (Guest)
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Hi everybody,

I want to create a testbench for a vhdl-ams code but I can't fix the 
errors in compilation.

Below, I show you how I usually write a component and his correspondant 
testbench in vhdl:

CODE:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity compteur is

  generic (N : integer:= 8);
  
  port(clk  : in std_logic;
       reset: in std_logic;
       load : in std_logic;
       data : in std_logic_vector (N-1 downto 0);
       flag : out bit;
       Q    : out std_logic_vector (N-1 downto 0));
       
end compteur;

architecture archi of compteur is

signal Qtmp: std_logic_vector (N-1 downto 0);
constant value : std_logic_vector := "00000111";

begin

  process (clk, reset)
  
  
    
  begin
    if clk 'event and clk = '1' then
      if reset = '0' then
        Qtmp <= (others => '0');
      
      elsif load ='1' then Qtmp <= data;
      
      else Qtmp <= Qtmp + 1;
        
      end if;
    
    end if;
        
  end process;

Q <= Qtmp;
flag <= '1' when Qtmp = value else '0';

end archi;

TESTBENCH:
Library IEEE;
Use IEEE.std_logic_1164.all;
library work;
use work.all;

entity compteur_tb is
end compteur_tb;

architecture archi of compteur_tb is
  
component compteur

  generic (N : integer:= 8);

  port(clk  : in std_logic;
       reset: in std_logic;
       load : in std_logic;
            data : in std_logic_vector (N-1 downto 0);
       flag : out bit;
       Q    : out std_logic_vector (N-1 downto 0));
       
end component;
  
signal clk  : std_logic;
signal reset: std_logic;
signal load : std_logic;
signal data : std_logic_vector (7 downto 0);
signal flag : bit;
signal Q    : std_logic_vector (7 downto 0);

constant T : time := 50 ns;

begin
  uut: compteur port map (clk => clk, reset => reset, load => load, data => data, flag => flag, Q => Q);

  clk_proc: process
  begin
  
    loop
      clk <= '0';
       wait for T/2;
       clk <= '1';
       wait for T/2;
    end loop;
  end process clk_proc;

      
  stimuli: process
  begin
  
    reset <= '0';
    load <= '1';
    data <= "00000011";
    wait for 40 ns;
    reset <= '1';
    load <= '1';
    wait for 100 ns;
    reset <= '1';
    load <= '0';
    wait for 200 ns;
    reset <= '1';
    load <= '0';
    wait for 100 ns;
    reset <= '1';
    load <= '0';
    wait for 200 ns;    
    reset <= '0';
    load <= '0';
    wait for 150 ns;
          
    assert false report "NONE. End of simulation." severity
    failure;
    wait for 100 us;
    
    
  end process stimuli;
  
end archi;

Now in vhdl-ams:
library ieee;
use ieee.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;

entity comparateur is 

  generic (level : real := 2.5;   -- seuil
     vcc   : real := 5.0;   -- etat haut sortie
     gnd   : real := 0.0);  -- etat bas sortie

  port(terminal e: electrical;  -- entree analogique
             signal   s: out real); -- sortie numerique

end comparateur;

architecture archi of comparateur is 

quantity v across e;       -- across quantity to ground

begin 

     s <= vcc when v'Above(level) -- v > level 
     else gnd;                    -- v < level

end archi;

library ieee;
use ieee.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library st_lib;
use st_lib.all;

entity comparateur_tb is
end entity comparateur_tb;

architecture archi of comparateur_tb is

component comparateur

  generic (level : real := 2.5;   -- seuil
     vcc   : real := 5.0;   -- etat haut sortie
     gnd   : real := 0.0);  -- etat bas sortie
  
  port(terminal e: electrical;
       signal s: out real);
       
end component;

signal e : electrical;
signal s: real;

constant T : time := 10 ns;

begin

  uut: comparateur port map (e => e, s => s);

  stimuli: process
  begin

    loop
      e <= 5.0;
       wait for T/2;
       e <= 0.0;
       wait for T/2;
  
    end loop;
      
    assert false report "NONE. End of simulation." severity
    failure;
    wait for 100 us;

  end process stimuli;

end archi;

And when I compile testbench I'm getting these errors:

ncvhdl -work st_lib -ams -message ../sources/comparateur_ent.
vhdl ../sources/comparateur_arch.vhdl ../sources/comparateur_tb.vhdl
ncvhdl: 13.10-s013: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
../sources/comparateur_ent.vhdl:
        errors: 0, warnings: 0
../sources/comparateur_arch.vhdl:
        errors: 0, warnings: 0
../sources/comparateur_tb.vhdl:
signal e : electrical;
                    |
ncvhdl_p: *E,EXPTYM (../sources/comparateur_tb.vhdl,24|20): type mark 
expected [
4.2].
        uut: comparateur port map (e => e, s => s);
                                        |
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,31|33): identifier 
(E) is no
t declared [10.3].
                        e <= 5.0;
                        |
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,37|3): identifier 
(E) is not
 declared [10.3].
                        e <= 0.0;
                        |
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,39|4): identifier 
(E) is not
 declared [10.3].
        errors: 4, warnings: 0


Do you know why and how to fix it ?

Even if this is no comparaison between compteur (counter) and 
comparateur (comparator), I show you that to see how I do usually.

Thanks in advance!

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