Forum: FPGA, VHDL & Verilog Counter in verilog

Author: Nisarg Shah (shahnisarg0796)
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Hello all,

I am new in verilog and trying to make counter code in verilog.
My requirement is like this...
for one 3 bit counter it's initial value is 0 but for other 3 bit 
counter the initial value is taken from user input and it will go on 
increasing till the maximum and then restart from zero.The clk is same 
for both case.

Example: If my initial value from user for counter2 is 011 for first 8 
clock pulse and for next 8 pulse it is 101 then output should be as 
           counter1 000,001,010,011,100,101,110,111,  000,001,..
           counter2 011,100,101,110,111,000,001,010,  101,110,..

The code which I tried for that is as follows but not got the correct 
result ,so please help me to find out the mistake in code:

module counter (clk,x,cnt1,cnt2);

input clk;
input [2:0] x;    // user input for counter2
output reg [2:0] cnt1,cnt2;

initial cnt1 = 0;
initial cnt2 = x;
always @(posedge clk)
   if(cnt1 == 7)
      cnt1 <= 0;
      cnt1 <= cnt1 + 1;
always @(posedge clk)
   if (cnt1 == 0)
      cnt2 <= x;
   else if (cnt2 == 7)
      cnt2 <= 0;
      cnt2 <= cnt2 + 1;



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