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Forum: FPGA, VHDL & Verilog Tri state buffer


Author: vhdl newbie (Company: none) (pranoy)
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library ieee;
use ieee.std_logic_1164.all;

entity tristate_buffer is 
port (enable: in std_logic;
d_in: in std_logic_vector ( 7 downto 0 ) ;
d_out: out std_logic_vector (7 downto 0 )) ;
end tristate_buffer;

architecture behavioral of tristate_buffer is
begin
process (enable,d_in)
begin
if (enable = 1) then
d_out <= d_in;
else
d_out <= (zzzzzzzz);
end if;
end process;
end behavioral;

what is the error in this program?
i get the following errors when i compile it in modelsim

tri_state_buffer.vhd(14): near "?": syntax error
tri_state_buffer.vhd(17): near "?": syntax error

Author: Schlumpf (Guest)
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Vectors: "ZZZZZZ" and not `ZZZZZZ´
Single Signals: '1' and not `1´

Author: vhdl newbie (Company: none) (pranoy)
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Thanks
library ieee;
use ieee.std_logic_1164.all;


entity tristate_buffer is 
port (enable: in std_logic;
d_in: in std_logic_vector ( 7 downto 0 ) ;
d_out: out std_logic_vector (7 downto 0 )) ;
end tristate_buffer;

architecture behavioral of tristate_buffer is
begin
process (enable,d_in)
begin
if (enable = '1') then
d_out <= d_in;
else
d_out <= ("zzzzzzzz");
end if;
end process;
end behavioral;

now the program is like this.
but new errors are coming like

tri_state_buffer.vhd(19): String literal has a character 'z' not in the 
enumeration type ieee.std_logic_1164.std_logic.

tri_state_buffer.vhd(22): VHDL Compiler exiting

pls help

Author: vhdl newbie (Company: none) (pranoy)
Posted on:

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THANKS

Got it.

The high impedence should be Z instead of z. :)

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