Forum: FPGA, VHDL & Verilog Modelsim simulation for Verilog

Author: Karim Ali (karim_2008)
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Hi all,
I am trying to simulate in Modelsim a xilinx video IP core (AXI to XVSI) 
using a do file (AXI_VidOut.do) and when I force the input video data 

     force s_axis_video_tdata  -deposit 16#0 20, 16#AABBCC 40, 16#AAAACC 

I found in the wave editor that s_axis_video_tdata was stuck to value 
16#AAAACC from 0 ns to the end of the simulation without changing
I attached the files to test if possible


Author: Tom Fairbairn (Company: Grasshopper) (tom_fairbairn)
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I can't open you're RAR file so I'll have to guess, but there are two 
immediate possibilities:

1) What is your `timescale?  You haven't specified "ns" in your force 
command time specifications so it's possible the force is being applied 
after 60ps, which you might not notice in your waveform.

2) Is there something else applying values to s_axis_video_tdata?  force 
-deposit only forces the value until something else drives a different 
value on to the net.

Hope that helps,

Author: Karim Ali (karim_2008)
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Thanks Tom
it was as u said about the timescale
actually before when I did simulations, I specified only the run 
duration and the clk in ns and it works
but it seems that this time the default configurations had been modified 
and I got that strange behavior



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